TDA8718 Datasheet, PDF (8/16 Pages) NXP Semiconductors – 8-bit high-speed analog-to-digital converter

Philips Semiconductors
8-bit high-speed analog-to-digital converter
Product specification
TDA8718
Notes to the “Characteristics”
1. Voltage offset BOTTOM (V_osB) is the difference between the analog input which produces data outputs equal to 00
and the reference voltage BOTTOM (V_RB) at T_amb = 25 °C. Voltage offset TOP (V_osT) is the difference between
reference voltage TOP (V_RT) and the analog input which produces data outputs equal to FF, at T_amb = 25 °C.
2. The analog input is not internally biased. It should be externally biased between V_RT and V_RB levels.
3. Full-scale sine wave; f_i = 4.43 MHz; f_clk = 100 MHz.
4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period.
The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
5. TDA8718 can only withstand one or two 100K ECL loads in order to work out timings at the maximum sampling
frequency. It is recommended to minimize the printed circuit-board load by implementing the load device as close as
possible to the TDA8718.
Table 1 Output coding and input voltage (typical values; referenced to AGND.
STEP
Underflow
0
1
.
.
.
254
255
Overflow
BINARY OUTPUT BITS
V_I
O/UF
D5
D4
D3
D2
D1
D0
< −40 Ω × I_RT
1
0
0
0
0
0
0
−40 Ω × I_RT
0
0
0
0
0
0
0
.
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
1
1
1
1
1
0
−8 Ω × I_RT
0
1
1
1
1
1
1
> −8 Ω × I_RT
1
1
1
1
1
1
1
handbook, full pagewidth
CLK
VI
DATA
OF/UF
sample N
sample N + 1 sample N + 2
50 %
DATA
N-2
t _ds
DATA
N-1
DATA
N
th
DATA
N+1
50 %
MSA666
June 1994
Fig.4 Timing diagram.
8