TDA8712 Datasheet, PDF (8/24 Pages) NXP Semiconductors – 8-bit digital-to-analog converters

Philips Semiconductors
8-bit digital-to-analog converters
Product specification
TDA8712; TDF8712
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Switching characteristics (f_clk = 50 MHz; notes 4 and 5; see Figs 3, 4 and 5)
t_SU;DAT
t_HD;DAT
t_PD
t_S1
data set-up time
data hold time
propagation delay time
settling time 1
−0.3
−
−
ns
2.0
−
−
ns
−
−
1.0
ns
10% to 90% full-scale −
change to ±1 LSB
1.1
1.5
ns
t_S2
settling time 2
10% to 90% full-scale −
change to ±1 LSB
6.5
8.0
ns
t_d
input to 50% output delay time
−
3.0
5.0
ns
Output transients (glitches; f_clk = 50 MHz; note 6; see Fig.6)
E_g
glitch energy from code
transition 127 to 128 −
−
30
LSB⋅ns
Notes
1. D0 to D7 are connected to V_CCD and CLK is connected to DGND.
2. The analog output voltages (V_OUT and V_OUT) are negative with respect to V_CCA (see Table 1). The output resistance
between V_CCA and each of these outputs is typically 75 Ω.
3. The −3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).
4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load
impedance greater than 75 Ω is connected between V_OUT or V_OUT and V_CCA. The specified values have been
measured with an active probe between V_OUT and AGND. No further load impedance between V_OUT and AGND has
been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable (independent
of input data variations) during the HIGH level of the clock (CLK = HIGH). During a LOW-to-HIGH transition of the
clock (CLK = LOW), the DAC operates in the transparent mode (input data will be directly transferred to their
corresponding analog output voltages; see Fig.5.
5. The data set-up time (t_SU;DAT) is the minimum period preceding the rising edge of the clock that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge of the clock and still be recognized. The data hold time (t_HD;DAT) is the minimum period following the rising
edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time indicates
that the data may be released prior to the rising edge of the clock and still be recognized.
6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at the
input transition between code 127 and 128 and on the falling edge of the clock.
June 1994
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