TDA4681 Datasheet, PDF (8/28 Pages) NXP Semiconductors – Video processor with automatic cut-off and white level control

Philips Semiconductors
Video processor with automatic cut-off
and white level control
Product specification
TDA4681
AUTO-INCREMENT
The auto-increment format enables quick slave receiver
initialization by one transmission, when the I²C-bus control
bit BREN = 0 (see control register bits of Table 1).
If BREN = 1 auto-increment is not possible.
If the auto-increment format is selected, the MAD byte is
followed by a SAD byte and by the data bytes of
consecutive subaddresses (see Fig.6).
All subaddresses from 00H to 0FH are automatically
incremented, the subaddress counter wraps round from
0FH to 00H. Reserved subaddresses 0BH, 0EH and 0FH
are treated as legal but have no effect. Subaddresses
outside the range 00H and 0FH are not acknowledged by
the device and neither auto-increment nor any other
internal operation takes place (for versions V1 to V5
subaddresses outside the range 00H and 0FH are
acknowledged but neither auto-increment nor any other
internal operation takes place).
Subaddresses are stored in the TDA4681 to address the
following parameters and functions (see Table 1):
• Brightness adjust
• Saturation adjust
• Contrast adjust
• Hue control voltage
• RGB gain adjust
• RGB reference voltage levels
• Peak drive limiting adjust
• Control register functions.
The data bytes D7 to D0 (see Table 1) provide the data of
the parameters and functions for video processing.
CONTROL REGISTER 1
VBWx (Vertical Blanking Window):
x = 0, 1 or 2. VBWx selects the vertical blanking interval
and positions the measurement lines for cut-off and
white level control.
The actual lines in the vertical blanking interval after the
start of the vertical pulses selected as measurement lines
for cut-off and white level control are shown in Table 2.
The standards marked with (*) are for progressive line
scan at double line frequency (2f_L), i.e. approximately
31 kHz.
NMEN (NTSC Matrix Enable):
0 = PAL/SECAM matrix
1 = NTSC matrix.
WPEN (White Pulse Enable):
0 = white measuring pulse disabled
1 = white measuring pulse enabled.
BREN (Buffer Register Enable):
0 = new data is executed as soon as it is received
1 = data is stored in buffer registers and is transferred to
the data registers during the next vertical blanking
interval.
The I²C-bus transceiver does not accept any new data
until this data is transferred into the data registers.
DELOF (Delay Off) delays the leading edge of clamping
pulses:
0 = delay enabled
1 = delay disabled.
SC5 (SandCastle 5 V):
0 = 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.
CONTROL REGISTER 2
FSON2 (Fast Switch 2 ON)
FSDIS2 (Fast Switch 2 Disable)
FSON1 (Fast Switch 1 ON)
FSDIS1 (Fast Switch 1 Disable)
The RGB input signals are selected by FSON2 and
FSON1 or FSW₂ and FSW₁:
• FSON2 has priority over FSON1
• FSW₂ has priority over FSW₁
• FSDIS1 and FSDIS2 disable FSW₁ and FSW₂
(see Table 3).
BCOF (Black level Control Off):
0 = automatic cut-off control enabled
1 = automatic cut-off control disabled; RGB outputs are
clamped to fixed DC levels.
FSBL (Full Screen Black Level):
0 = normal mode
1 = full screen black level (cut-off measurement level
during full field).
FSWL (Full Screen White Level):
0 = normal mode
1 = full screen white level (white measurement level
during full field).
1997 Mar 04
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