SCC2681T Datasheet, PDF (8/15 Pages) NXP Semiconductors – Dual asynchronous receiver/transmitter (DUART)

Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC2681T
AC ELECTRICAL CHARACTERISTICS^{1, 2, 3, 4}
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Typ
Max
Reset timing (see Figure 3)
t_RES
Reset pulse width
Bus timing (see Figure 4) (Note 5)
1.0
–
–
µs
t_AVEL
t_ELAX
t_RLRH
t_EHEL
t_RLDA
t_RLDV
t_RHDI
t_RHDF
t_WLWH
t_DVWH
t_WHDI
A0–A3 set-up to RDN and CEN, or WRN and CEN LOW
RDN and CEN, or WRN and CEN LOW to A0–A3 invalid
RDN and CEN LOW to RDN or CEN HIGH
CEN HIGH to CEN LOW^{6, 7}
CEN and RDN LOW to data outputs active
CEN and RDN LOW to data valid
CEN or RDN HIGH to data invalid
CEN or RDN HIGH to data outputs floating
WRN and CEN LOW to WRN or CEN HIGH
Data input valid to WRN or CEN HIGH
WRN or CEN HIGH to data invalid
Port timing (see Figure 5)
0
–
–
ns
100
–
–
ns
120
–
–
ns
110
–
–
ns
15
–
–
ns
–
–
100
ns
10
–
–
ns
–
–
65
ns
75
–
–
ns
35
–
–
ns
15
–
–
ns
t_PS
Port input set-up time before RDN LOW
t_PH
Port input hold time after RDN HIGH
t_PD
Port output valid after WRN HIGH
Interrupt timing (see Figure 6)
0
–
–
ns
0
–
–
ns
–
–
200
ns
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
t_IR
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
–
–
200
ns
–
–
200
ns
–
–
200
ns
–
–
200
ns
–
–
200
ns
–
–
200
ns
Clock timing (see Figure 7)
t_CLK
f_CLK
t_CTC
f_CTC
t_RX
f_RX
X1/CLK HIGH or LOW time
X1/CLK frequency
CTCLK (IP2) HIGH or LOW time
CTCLK (IP2) frequency⁸
RxC HIGH or LOW time
RxC frequency
(16×)⁸
(1×)⁸
90
2
55
0
55
0
3.6864
0
ns
4
MHz
ns
8
MHz
ns
8
MHz
1
MHz
t_TX
TxC HIGH or LOW time
f_TX
TxC frequency
(16×)⁸
(1×)⁸
110
ns
0
4
MHz
0
1
MHz
Transmit timing (see Figure 8)
t_TXD
TxD output delay from TxC external clock input on IP pin
t_TCS
Output delay from TxC LOW at OP pin to TxD data output
Receive timing (see Figure )
–
–
300
ns
0
–
100
ns
t_RXS
RxD data set-up time before RxC HIGH at external clock input on IP pin
200
–
–
ns
t_RXH
RxD data hold time after RxC HIGH at external clock input on IP pin
25
–
–
ns
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V_CC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.0 V. All time measurements are referenced at input
voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
2004 Apr 06
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