SC16C550 Datasheet, PDF (8/52 Pages) NXP Semiconductors – Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Table 2:
Symbol
RCLK
Pin description…continued
Pin
Type
PLCC44 LQFP48 DIP40
10
5
9
I
IOR, IOR 24, 25 19, 20 21, 22 I
RI
43
41
39
I
RTS
36
32
32
O
RXRDY
32
29
29
O
RX
11
7
10
I
TX
13
8
11
I
TXRDY
27
23
24
O
Description
Receiver clock. RCLK is the 16× baud rate clock for the receiver
section of the UART.
Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to read
status information or data from a selected UART register. Only one of
these inputs is required for the transfer of data during a read operation;
the other input should be tied to its inactive level (i.e., IOR tied LOW or
IOR tied HIGH).
Ring indicator. RI is a modem status signal. Its condition can be
checked by reading bit 6 (RI) of the modem status register. Bit 2
(TERI) of the modem status register indicates that RI has transitioned
from a LOW to a HIGH level since the last read from the modem status
register. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.
Request to send. When active, RTS informs the modem or data set
that the UART is ready to receive data. RTS is set to the active level by
setting the RTS modem control register bit and is set to the inactive
(HIGH) level either as a result of a Master Reset or during loop mode
operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS
mode, RTS is set to the inactive level by the receiver threshold control
logic.
Receiver ready. Receiver direct memory access (DMA) signaling is
available with RXRDY. When operating in the FIFO mode, one of two
types of DMA signaling can be selected using the FIFO control register
bit 3 (FCR[3]). When operating in the 16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports
multi-transfer DMA in which multiple transfers are made continuously
until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0
or FCR0 = 1, FCR3 = 0), when there is at least one character in the
receiver FIFO or receiver holding register, RXRDY is active (LOW).
When RXRDY has been active but there are no characters in the FIFO
or holding register, RXRDY goes inactive (HIGH). In DMA mode 1
(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been
reached, RXRDY goes active (LOW); when it has been active but there
are no more characters in the FIFO or holding register, it goes inactive
(HIGH).
Serial data input. RX is serial data input from a connected
communications device.
Serial data output. TX is composite serial data output to a connected
communication device. TX is set to the marking (HIGH) level as a
result of Master Reset.
Transmitter ready. Transmitter DMA signaling is available with
TXRDY. When operating in the FIFO mode, one of two types of DMA
signaling can be selected using FCR[3]. When operating in the
16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multi-transfer DMA in which multiple transfers
are made continuously until the transmit FIFO has been filled.
9397 750 11619
Product data
Rev. 05 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8 of 52