SAA4955TJ Datasheet, PDF (8/28 Pages) NXP Semiconductors – 2.9-Mbit field memory

Philips Semiconductors
2.9-Mbit field memory
Product specification
SAA4955TJ
from the new address block at the next positive transition
of SRCK. The complete read block access entry sequence
is finished after the 20th read latency cycle.
The LOW-to-HIGH transition on RSTR required at the
beginning of the sequence should not be repeated.
Additional LOW-to-HIGH transitions on RSTR would
disable read block address mode and reset the read
pointer.
operations (SWCK) followed by a reset write operation
(RSTW). Read and write initialization may be performed
simultaneously.
If initialization starts earlier than the recommended 100 µs
after power-up, the initialization sequence described
above must be repeated, starting with an additional reset
read operation and an additional reset write operation after
the 100 µs start-up time.
DATA OUTPUTS: Q0 TO Q11 AND READ CLOCK: SRCK
The new data is shifted out of the data output registers on
the rising edge of the SRCK read clock provided RE and
OE are HIGH. Data output pins are low impedance if OE is
HIGH. If OE is LOW, the data outputs are high impedance
and the data output bus may be used by other devices.
Data output hold (t_h(Q)) and access (t_ACC) times are
referenced to the positive transition of SRCK. The output
data becomes valid after access time interval t_ACC (see
Fig.11).
Data output pins Q0 to Q11 are TTL compatible with the
restriction that when the outputs are high impedance, they
must not be forced higher than V_DD(O) + 0.5 V or 5.0 V
absolute. The output data has the same polarity as the
incoming data at inputs D0 to D11.
READ ENABLE: RE
RE is used to increment the read pointer. Therefore, RE
needs to be HIGH at the positive transition of SRCK. When
RE is LOW, the read pointer is not incremented. RE set-up
(t_su(RE)) and hold (t_h(RE)) times are referenced to the
positive edge of SRCK (see Fig.13).
OUTPUT ENABLE: OE
OE is used to enable or disable data outputs Q0 to Q11.
The data outputs are enabled (low impedance) if OE is
HIGH. OE LOW disables the data output pins (high
impedance). Incrementing of the read pointer does not
depend on the status of OE. OE set-up (t_su(OE)) and hold
(t_h(OE)) times are referenced to the positive edge of SRCK
(see Fig.14).
Power-up and initialization
Reliable operation is not guaranteed until at least 100 µs
after power-up, the time needed to stabilize V_DD within the
recommended operating range. After the 100 µs power-up
interval has elapsed, the following initialization sequence
must be performed: a minimum of 12 dummy read
operations (SRCK cycles) followed by a reset read
operation (RSTR), and a minimum of 12 dummy write
Old and new data access
A minimum delay of 40 SWCK clock cycles is needed
before newly written data can be read back from memory
(see Fig.15). If a reset read operation (RSTR) occurs in a
read cycle before a reset write operation (RSTW) in a write
cycle accessing the same memory location, then old data
will be read.
Old data will be read provided a data read cycle begins
within 20 pointer positions of the start of a write cycle. This
means that if a reset read operation begins within
20 SWCK clock cycles after a reset write operation, the
internal buffering of the SAA4955TJ will ensure that old
data will be read out (see Fig.16).
New data will be read if the read pointer is delayed by
40 pointer positions or more after the write pointer. Old
data is still read out if the write pointer is less than or equal
to 20 pointer positions ahead of the read pointer (internal
buffering). A write pointer to read pointer delay of more
than 20 but less than 40 pointer positions should be
avoided. In this case, the old or the new data may be read,
or a combination of both.
In random read and write block access modes, the
minimum write-to-read new data delay of 40 SWCK clock
cycles must be inserted for each block.
Memory arbitration logic and self-refresh
Since the data in the memory array is stored in DRAM
cells, it needs to be refreshed periodically. Refresh is
performed automatically under the control of internal
memory arbitration logic which is clocked by a free running
clock oscillator. The memory arbitration logic controls
memory access for read, write and refresh operations.
It uses the contents of the write, read and refresh address
counters to access the memory array to load data from the
parallel write register, store data in the parallel read
register, or to refresh stored data. The values in these
counters correspond to block addresses.
1999 Apr 29
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