SAA2505H Datasheet, PDF (8/28 Pages) NXP Semiconductors – Digital multi-channel audio IC DUET

Philips Semiconductors
Digital multi-channel audio IC (DUET)
Preliminary specification
SAA2505H
CLOCK BUILD-UP
Up to four clocks provide the timing information for the
SAA2505H. These are as follows:
1. Data source clock
2. Data processing clock
3. I²C-bus data/control clock
4. Data sink clock.
Data source clock
Clocking of the input data is derived from the serial clock
input at pin 58 and is compliant with the I²S-bus and EIAJ
transfer formats. The ports are capable of operating at
normal, double and quad speed.
Data processing clock
This clock is used for data processing and internal data
transfer. The clock can either be provided by an external
clock generator having a duty cycle between 40 and 60%
or by using the internal crystal clock generator and an
external crystal. The external clock should be connected
between pins 42 (CLKI) and 43 (CLKO) (see Fig.11).
To use the internal clock a 35 MHz crystal operating on the
3rd harmonic must be connected between pins 42 and 43
(CLKI and CLKO).
A buffered version of this clock is available at pin 39
(SYSCLK). This can be optionally disabled or, a divided
version (4, 2 and 1) of the clock input at pin 42 (CLKI) can
be made available.
I²C-bus data/control clock
The I²C-bus control logic supports I²C-bus clock speeds
up to 400 kHz. This is supplied to pin 63 (SCL). If the
SAA2505H is in the stand-alone mode (pin 1 HIGH) no
I²C-bus clock needs to be supplied.
Data sink clock
The data sink clock source is dependant on the mode of
operation of the I²S-bus output ports.
In the master mode the I²S-bus clock is derived form an
external 256 or 384f_s source connected to pin 45 (ACLK).
This is internally divided and used to drive the serial clock
at pins 15 and 31 (SCK and SCKO3). To ensure that the
digital outputs poses good timing qualities (jitter and
wander) pin 45 should be a connected to a high quality
timing source.
In the I²S-bus slave mode the output data is clocked to
pin 15. This can either be the serial clock input at pin 58
(SCKI) or a suitable external clock. When in slave mode
the signal at pin 15 is replicated at pin 31.
FUNCTIONAL DESCRIPTION
Data sinks
Coded audio data or PCM audio data can be input to both
DSPs from two slave-only serial interfaces capable of
receiving data in either I²S-bus or EIAJ formats. Both serial
interfaces use the same serial clock (pin 58) and word
select input (pin 54). The serial clock must be at least 32f_s.
Serial data is applied to pins 56 and 57 (SDI0 and SDI1).
These pins are mode shared between the I²S-bus and
EIAJ formatted serial data. Port mode selection is
achieved via the I²C-bus interface, see Table 3.
I²S-BUS FORMATTED SPDIF INFORMATION
In the I²S-bus mode ‘big-endian’ data is received, MSB
justified to 1 clock period after a falling edge of the word
select output. The data stream should be formatted
according to “IEC 60958 - SPDIF” including the extensions
for non-PCM encoded audio data (“IEC 61937”).
AC-3 and MPEG coded data is formatted in 16-bit words.
These words are expected at a sample rate (f_s) of 48 kHz
and thus a minimum serial clock of 1.536 MHz; two 16-bit
words per word select period. If the transmission word
length is in excess of 16 bits all additional bits are
discarded.
PCM sample lengths of up to 20-bit words are supported
with sample rates of 44.1 and 48 kHz. This mode is used
to transfer PCM and PCM with Dolby pro-logic encoded
data. Word select LOW corresponds to transmission of
data for the left channel, word select HIGH corresponds to
transmission of data for the right channel.
Pin 55 (SDBI) is reserved for a multi-channel extension to
the I²S-bus and is currently not supported.
1998 Mar 10
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