SA58643 Datasheet, PDF (8/16 Pages) NXP Semiconductors – Excellent overload capability

NXP Semiconductors
SA58643
Single-Pole Double-Throw (SPDT) switch
13. Application information
13.1 Evaluation demo board
The typical applications schematic and printed-circuit board layout of the SA58643
evaluation board is shown in Figure 19. The layout of the board is simple, but a few
cautions need to be observed. The input and output traces should be 50 Ω. The
placement of the AC bypass capacitor is extremely critical if a symmetric isolation
between the two channels is desired. The trace from pin 7 (AC_GND) should be drawn
back towards the package and then be routed downwards. The capacitor should be
placed straight down as close to the device as practical. For better isolation between the
two channels at higher frequencies, it is also advisable to run the two output/input traces
at an angle. This also minimizes any inductive coupling between the two traces. The
power supply bypass capacitor should be placed close to the device. Figure 5 shows the
frequency response of the SA58643. The loss matching between the two channels is
excellent to 1.2 GHz as shown in Figure 7.
V_DD
+5 V
0.1 µF
INPUT
1
ENCH1
2
GND ₃
4
0.01 µF
a. Evaluation board schematic
DP package
SA58643
0.01 µF
8
AC_GND
7
6 ^{GND 0.01 µF}
5
002aab691
0.01 µF
OUT1
OUT2
top view
bottom view
ENCH1
C2
C1
C6
C3 OUT1
U1 _{Analog GND}
C5
C4 ^OUT2
ENCH1
C2
C1
C6
C3 OUT1
U1 _{Analog GND}
C5
C4 ^OUT2
SA58643 TSSOP8
A
#30007-A50 _B
Test Line
b. SA58643 board layout
Fig 19. Evaluation board and layout
SA58643 TSSOP8
A
#30007-A50 _B
Test Line
002aab692
SA58643_1
Product data sheet
Rev. 01 — 20 November 2006
© NXP B.V. 2006. All rights reserved.
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