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PCK2022RA Datasheet, PDF (8/14 Pages) NXP Semiconductors – CK00 (100/133 MHz) spread spectrum differential system clock generator
Philips Semiconductors
CK00 (100/133 MHz) spread spectrum differential
system clock generator
Product data
PCK2022RA
AC ELECTRICAL CHARACTERISTICS
VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz
Host clock outputs
Tamb = 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
tPKP
HOST CLK average period
7.5
7.65
10.0
10.2
Abs Min Period Absolute minimum host clock period
7.35
N/A
9.85
N/A
tRISE
tFALL
tJITTER
DUTY CYCLE
HOST CLK rise time
HOST CLK fall time
HOST_CLK cycle-to-cycle jitter
Output duty cycle
175
700
175
700
175
700
175
700
—
150
—
150
45
55
45
55
tSKEW
Rise/Fall Match-
ing
HOST CLK pin-to-pin skew
Rise and Fall time matching
—
150
—
150
—
20%
—
20%
Vcrossover
REFER TO NOTES ON PAGE 9.
40% VOH 55% VOH 40% VOH 55% VOH
UNITS
NOTES
ns
11, 14, 20
ns
11, 14, 20
ns
11, 15, 20
ps
11, 15, 20
ps 11, 12, 14, 20
%
11, 14, 20
ps
11, 14, 20
11, 16, 20
V
11, 14, 20
IOCLK outputs
Tamb = 0 to +70 °C
SYMBOL
PARAMETER
tPKP
IOCLK period
tPKH
IOCLK HIGH time
tPKL
IOCLK LOW time
tRISE
IOCLK rise time
tFALL
IOCLK fall time
tJITTER
Cycle-to-cycle jitter
DUTY CYCLE Output duty cycle
REFER TO NOTES ON PAGE 9.
LIMITS
33 MHz MODE
66 MHz MODE
MIN
MAX
MIN
MAX
30.0
N/A
15.0
N/A
12.0
N/A
6.0
N/A
12.0
N/A
6.0
N/A
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
—
200
—
200
45
55
45
55
UNITS
NOTES
ns
2, 3, 9, 20
ns
5, 10, 20
ns
6, 10, 20
ns
8, 20
ns
8, 20
ps
18, 20
%
18, 20
USB clock output, 48MHz
Tamb = 0 to +70 °C; lump capacitance test load = 20 pF
SYMBOL
PARAMETER
f
Frequency, actual
fD
tHKL
tRISE
tFALL
tJITTER
DUTY CYCLE
Deviation from 48 MHz
3V48MHZCLK LOW time
3V48MHZCLK rise time
3V48MHZCLK fall time
Cycle-to-cycle jitter
Output duty cycle
REFER TO NOTES ON PAGE 9.
LIMITS
48 MHz MODE
MIN
MAX
48.08
+167
5.05
N/A
1.0
4.0
1.0
4.0
—
250
45
55
UNITS
MHz
ppm
ns
ns
ns
ps
%
NOTES
4
4
20
8, 20
8, 20
18, 20
18, 20
2003 Jul 31
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