HEF4751V Datasheet, PDF (8/10 Pages) NXP Semiconductors – Universal divider

Philips Semiconductors
Universal divider
Product specification
HEF4751V
LSI
CASCADING OF U.D.s (see also Fig. 8)
A U.D. is programmed into the ‘slave’ mode by the
programme input data: n_2A = 11, n_2B = 10,
n_3A = n_4A = n_3B = n_4B = n_5B = 0. A U.D. operating in the
slave mode performs the function of two extra
programmable stages C2’ and C3’ to a ‘master’ (not slave)
mode operating U.D. More slave U.D.s may be used,
every slave adding two lower significant digits to the
system.
Output OFB₃ is converted to the borrow output of the
programme data subtractor, which is valid after fetch
period 5. Input SI is the borrow input (both in master and in
slave mode), which has to be valid in fetch period 0. Input
SI has to be connected to output OFB₃ of a following slave,
if not present, to LOW. For proper transfer of the borrow
from a lower to a higher significant U.D. subtractor, the
U.D.s have to be programmed sequentially in order of
significance or synchronously if the programme is
repeated at least the number of U.D.s in the system.
Rate input RI and output OFS must be connected to rate
output OFB₁ and the input IN of the next slave U.D. The
combination thus formed retains the full programmability
and features of one U.D.
OUTPUT (see also Fig.7)
The normal output of the U.D. is the slow output OFS,
which consists of evenly spaced LOW pulses. This output
is intended for accurate phase comparison. If a better
frequency acquisition time is required, the fast output OFF
can be used. The output frequency on OFF is a factor
M ⋅ H higher than the frequency on OFS. However, phase
jitter of maximum ± 1 system input period occurs at OFF,
since the division ratio of the counters preceding OFF are
varied by slow feedback pulse trains from rate selectors
following OFF.
Fig.7 Timing diagram showing output pulses.
January 1995
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