HEF4094BTD-T Datasheet, PDF (8/20 Pages) NXP Semiconductors – 8-stage shift-and-store register

NXP Semiconductors
HEF4094B
8-stage shift-and-store register
Table 7. Dynamic characteristics …continued
V_SS = 0 V; T_amb = 25 C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter
Conditions V_DD
Extrapolation formula
t_PLZ
LOW to OFF-state OE to QPn;
5V
propagation delay
see Figure 9 _{10 V}
15 V
t_su
set-up time
D to CP;
5V
see Figure 10 _{10 V}
15 V
t_h
hold time
D to CP;
5V
see Figure 10 _{10 V}
15 V
t_W
pulse width
minimum LOW 5 V
clock pulse;
see Figure 7
10 V
15 V
minimum HIGH 5 V
strobe pulse;
see Figure 8
10 V
15 V
f_max
maximum frequency see Figure 7 5 V
10 V
15 V
Min Typ Max Unit
-
80 160 ns
-
40 80 ns
-
30 60 ns
60 30 -
ns
20 10 -
ns
15 5
-
ns
+5 15 -
ns
20 5
-
ns
20 5
-
ns
60 30 -
ns
30 15 -
ns
24 12 -
ns
40 20 -
ns
30 15 -
ns
24 12 -
ns
5
10 -
MHz
11 22 -
MHz
14 28 -
MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C_L in pF).
Table 8. Dynamic power dissipation
V_SS = 0 V; t_r = t_f  20 ns; T_amb = 25 C.
Symbol Parameter
V_DD
Typical formula for P_D (W)
P_D
dynamic power 5 V
P_D = 2100  f_i + (f_o  C_L)  V_DD2
dissipation
10 V
P_D = 9700  f_i + (f_o  C_L)  V_DD2
15 V
P_D = 26000  f_i + (f_o  C_L)  V_DD2
where:
f_i = input frequency in MHz,
f_o = output frequency in MHz,
C_L = output load capacitance in pF,
V_DD = supply voltage in V,
(f_o  C_L) = sum of the outputs.
HEF4094B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 29 August 2013
© NXP B.V. 2013. All rights reserved.
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