BUK108-50GL Datasheet, PDF (8/11 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK108-50GL
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.20. Test circuit for resistive load switching times.
VDD = VCL
LD
t _{p : adjust for correct ID}
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.23. Test circuit for inductive load switching times.
RESISTIVE TURN-ON
VDS / V
10
BUK108-50GL
td on
tr
5
10%
0
10%
VIS / V
ID / A
90%
0
10
20
time / us
Fig.21. Typical switching waveforms, resistive load.
V_DD = 13 V; R_L = 4 Ω; R_I = 50 Ω, T_j = 25 ˚C.
RESISTIVE TURN-OFF
10
td off
BUK108-50GL
VDS / V
VIS / V
tf
5
90%
90%
ID / A
10%
0
0
10
20
time / us
Fig.22. Typical switching waveforms, resistive load.
V_DD = 13 V; R_L = 4 Ω; R_I = 50 Ω, T_j = 25 ˚C.
INDUCTIVE TURN-ON
VDS / V
10
BUK108-50GL
td on
tr
5
90%
VIS / V
ID / A
10%
10%
0
0
10
20
time / us
Fig.24. Typical switching waveforms, inductive load.
V_DD = 13 V; I_D = 3 A; R_I = 50 Ω, T_j = 25 ˚C.
INDUCTIVE TURN-OFF
15
BUK108-50GL
VDS / V
10
td off
VIS / V
5
90%
tf
ID / A
90%
10%
0
0
10
20
time / us
Fig.25. Typical switching waveforms, inductive load.
V_DD = 13 V; I_D = 3 A; R_I = 50 Ω, T_j = 25 ˚C.
June 1996
8
Rev 1.000