ADC0820 Datasheet, PDF (8/14 Pages) National Semiconductor (TI) – 8-Bit High Speed μP Compatible A/D Converter with Track/Hold Function

Philips Semiconductors Linear Products
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
Product specification
ADC0820
FUNCTIONAL DESCRIPTION
General Operation
The ADC0820 uses two 4-bit flash A/D converters to make an 8-bit
measurement (Block Diagram). Each flash ADC is made up of 15
comparators which compare the unknown input to a reference
ladder to get a 4-bit result. To take a full 8-bit reading, one flash
conversion is done to provide the 4 most significant data bits (via the
MS flash ADC). Driven by the 4 MSBs, an internal DAC recreates an
analog approximation of the input voltage. This analog signal is then
subtracted from the input, and the difference voltage is converted by
a second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash converter.
This is accomplished by using the same resistor ladder for the A/D
as well as for generating the DAC signal. The DAC output is actually
the tap on the resistor ladder which most closely approximates the
analog input. In addition, the “sampled data” comparators used in
the ADC0820 provide the ability to compare the magnitudes of
several analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC, where the
signal to be converted is an analog difference.
The Sampled-Data Comparator
Each comparator in the ADC0820 consists of a CMOS inverter with
a capacitively-coupled input (Figure 4). Analog switches connect the
two comparator inputs to the input capacitor (C) and also connect
the inverter’s input and output. This device in effect now has one
differential input pair. A comparison requires two cycles, one for
zeroing the comparator, and another for making the comparison.
V1
C
A
V_O
V_S
V2
C_S
In the first cycle, one input switch and the inverter’s feedback switch
(Figure 4a) are closed. In this interval, C is charged to the
connected input (V1) less the inverter’s bias voltage (V_S,
approximately 1.6V). In the second cycle (Figure 4b), these two
switches are opened and the other (V2) input’s switch is closed. The
input capacitor now subtracts its stored voltage from the second
input and the difference is amplified by the inverter’s open loop gain.
The inverter’s input (V_S’) becomes
VȀ_SȀ
+
V_S
)
(V2
–
V1)
C
C
) C_S
and the output will go High or Low depending on the sign of V’_S’-V_S.
The actual circuitry used in the ADC0820 is a simple but important
expansion of the basic comparator described above. By adding a
second capacitor and another set of switches to the input (Figure 5),
the scheme can be expanded to make dual differential comparisons.
In this circuit, the feedback switch and one input switch on each
capacitor (Z switches) are closed in the zeroing cycle. A comparison
is then made by connecting the second input on each capacitor (S
switches) and opening all of the other switches. The change in
voltage at the inverter’s input, as a result of the change in charge on
each input capacitor, will now depend on both input signal
differences.
Architecture
In the ADC0820, 15 comparators are used in the MS and LS 4-bit
flash A/D converters. The MS (most significant) flash ADC also has
one additional comparator to detect input over-range. These two
sets of comparators operate alternately, with one group in its zeroing
cycle while the other is comparing.
V1
C
A
V_O
V_S
V2
C_S
• V_O = V_S
• V ON C = V1 – V_B
• C_S = SATRAY INPUT NODE CAPACITOR
• V_S = INVERTER INPUT BIAS VOLTAGE
a. Zeroing Phase
C
• V_S’ – V_S
= (V2 – V1)
–A
C
+
C_S
• V_O’ = _{C + CS [CV2 – CV1]}
• V_O’ IS DEPENDENT ON V2–V1
b. Compare Phase
Figure 4. Sampled Data Comparator
Z
R LADDER (V1)
S
V_IN (V2)
Z
ANALOG GND
(V3)
S
1/2 LSB (V4)
C1
Z
A
C_S VS
C2
V_O
V_O =
=
–A
[C1 (V2 – V1) + C2 (V4–V3)]
C1 + C2 + C_S
–A
C1 + C2 + C_S ^{[ ∆QC1 + ∆QC2]}
Figure 5. ADC0820 Comparator (From MS Flash ADC)
August 31, 1994
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