74HC7731 Datasheet, PDF (8/8 Pages) NXP Semiconductors – Quad 64-bit static shift register

Philips Semiconductors
Quad 64-bit static shift register
60
handbook, halfpage
CPD
(pF)
40
MLA166
20
0
0
0.2
0.4
0.6
duty factor
Fig.6 C_PD as a function of the duty factor.
Product specification
74HC/HCT7731
POWER DISSIPATION INFORMATION
The power dissipation per register operating at the same
frequency is given by:
P_D = (C_PD x V_CC2 x f_i) + (C_L + V_CC2 x f_o) + (I_pull-up x V_CC)
f_i
= clock input frequency
f_o
= data output frequency
C_L = output load capacitance in pF
V_CC = power supply voltage in V.
As P_D also depends on the frequency at which the
contents of the internal bits are changing, the value of C_PD
is a function of the duty factor (d_f) being the ration between
data and clock frequency, see Fig.6.
Example:
f_i
= 12 MHz
f_o
= 3 MHz
C_L = 25 pF
V_CC = 5 V
d_f
= 3/12 = 0.25
C_PD = 42.5 pF
P_D = (42.5 × 5² × 12) + (25 × 5² × 3) = 14625 µW
As the maximum allowable power dissipation in an SO
package at T_amb = 125 °C is 60 mW, it is allowed to apply
4 registers at the same time under these conditions.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
8