74HC283 Datasheet, PDF (8/8 Pages) NXP Semiconductors – 4-bit binary full adder with fast carry

Philips Semiconductors
4-bit binary full adder with fast carry
Product specification
74HC/HCT283
AC WAVEFORMS
APPLICATION INFORMATION
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.6 Waveforms showing the inputs (C_IN, A_n, B_n)
to the outputs (∑_n, C_OUT) propagation delays
and the output transition times.
Fig.7 3-bit adder.
Fig.8 2-bit and 1-bit adder.
Fig.9 5-input encoder.
Notes to Figs 7 to 10
Figure 7 shows a 3-bit adder using the “283”. Tying the
operand inputs of the fourth adder (A₃, B₃) LOW makes ∑₃
dependent on, and equal to, the carry from the third adder.
Based on the same principle, Figure 8 shows a method of
dividing the “283” into a 2-bit and 1-bit adder. The third
stage adder (A₂, B₂, ∑ ₂) is used simply as means of
transferring the carry into the fourth stage (via A₂ and B₂)
and transferring the carry from the second stage on ∑ ₂.
Note that as long as long as A₂ and B₂ are the same, HIGH
or LOW, they do not influence ∑ ₂. Similarly, when A₂ and
B₂ are the same, the carry into the third stage does not
influence the carry out of the third stage. Figure 9 shows a
method of implementing a 5-input encoder, where the
Fig.10 5-input majority gate.
inputs are equally weighted. The outputs ∑ ₀, ∑₁ and ∑ ₂
produce a binary number equal to the number inputs (I₁ to
I₅) that are HIGH. Figure 10 shows a method of
implementing a 5-input majority gate. When three or more
inputs (I₁ to I₅) are HIGH, the output M₅ is HIGH.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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