74F651A Datasheet, PDF (8/14 Pages) NXP Semiconductors – Transceivers/registers

Philips Semiconductors
Transceivers/registers
Product specification
74F651A/74F652A
AC ELECTRICAL CHARACTERISTICS FOR 74F651A
SYMBOL
PARAMETER
TEST CONDITION
f_max
Maximum clock frequency
t_PLH
Propagation delay
t_PHL
CPAB or CPBA to An or Bn
t_PLH
Propagation delay
t_PHL
An or Bn to Bn or An
t_PLH
Propagation delay
t_PHL
SAB or SBA to An or Bn
t_PZH
Output enable time
t_PZL
OEAB or OEBA to An or Bn
t_PHZ
Output disable time
t_PLZ
OEAB or OEBA to An or Bn
Waveform 1
Waveform 1
Waveform 2, 3
Waveform 2, 3
Waveform 7, 8
Waveform 7, 8
LIMITS
T_amb = +25°C
V_CC = +5.0V
C_L = 50pF, R_L = 500Ω
MIN TYP MAX
T_amb = 0°C to +70°C
V_CC = +5.0V ± 10%
C_L = 50pF, R_L = 500Ω
MIN
MAX
155 175
140
4.5 7.0 10.0
4.0
11.0
5.5 7.5 10.5
5.0
11.0
2.5
4.5
7.5
2.0
8.5
4.0
6.5
9.0
4.0
10.0
4.0 7.0 10.0
3.5
12.0
5.0 7.0 10.0
4.5
10.0
3.0
5.0
8.0
2.5
8.5
3.5
6.0
8.5
3.0
9.0
1.5
4.0
7.0
1.0
7.5
2.5
6.0
8.5
2.0
9.0
UNIT
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS FOR 74F651A
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T_amb = +25°C
V_CC = +5.0V
C_L = 50pF, R_L = 500Ω
MIN TYP MAX
T_amb = 0°C to +70°C
V_CC = +5.0V ± 10%
C_L = 50pF, R_L = 500Ω
MIN
MAX
t_su (H)
t_su (L)
Setup time, high or low
An or Bn to CPAB or CPBA
Waveform 4
3.5
4.0
4.0
4.5
t_h (H)
t_h (L)
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
t_su (H)
t_su (L)
Setup time, high or low
OEBA to OEAB or OEAB to OEBA
Waveform 5, 6
5.0
5.0
5.0
5.0
t_h (H)
t_h (L)
Hold time, high or low
OEBA to OEAB or OEAB to OEBA
Waveform 5, 6
0
0
0
0
t_w (H)
t_w (L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
4.5
3.5
4.5
4.0
Note to AC setup requirements for 74F651A:
1. Setup time is to protect against surge current caused by enabling 16 outputs (48mA per output) simultaneously.
UNIT
ns
ns
ns
ns
ns
1999 Jun 23
8