LPC1823JBD144E Datasheet, PDF (72/147 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB

NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
7.15.7 High-speed USB Host/Device interface with ULPI (USB1)
Remark: USB1 is available on the following parts: LPC185x and LPC183x. USB1 is not
available on the LPC182x and LPC181x parts.
The USB1 interface can operate as a full-speed USB host/device interface or can connect
to an external ULPI PHY for High-speed operation.
7.15.7.1 Features
• Complies with Universal Serial Bus specification 2.0.
• Complies with Enhanced Host Controller Interface Specification.
• Supports auto USB 2.0 mode discovery.
• Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
• Supports all full-speed USB-compliant peripherals.
• Supports interrupts.
• Supports Start Of Frame (SOF) frame length adjust.
• This module has its own, integrated DMA engine.
• USB interface electrical test software included in ROM USB stack.
7.15.8 LCD controller
Remark: The LCD controller is only available on parts LPC185x. LCD is not available on
parts LPC183x, LPC182x, and LPC181x.
The LCD controller provides all of the necessary control signals to interface directly to
various color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024  768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of
the displayed data) while still supporting many colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time required to operate the display.
7.15.8.1 Features
• AHB master interface to access frame buffer.
• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320  200, 320  240,
640  200, 640  240, 640  480, 800  600, and 1024  768.
• Hardware cursor support for single-panel displays.
LPC185X_3X_2X_1X
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 31 October 2012
© NXP B.V. 2012. All rights reserved.
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