TJA1043T Datasheet, PDF (7/27 Pages) NXP Semiconductors – High-speed CAN transceiver

NXP Semiconductors
TJA1043
High-speed CAN transceiver
7.1.3 Standby mode
Standby mode is the TJA1043’s first-level power saving mode, offering reduced current
consumption. In Standby mode, the transceiver is unable to transmit or receive data and
the low-power receiver is activated to monitor bus activity. The bus pins are biased at
ground level (via R_i). Pin INH is still active, so voltage regulators controlled by this pin will
also be active.
Pins RXD and ERR_N will reflect any active wake-up requests (provided that V_IO and
V_BAT are present).
7.1.4 Go-to-Sleep mode
Go-to-Sleep mode is the controlled route for entering Sleep mode. In Go-to-Sleep mode,
the transceiver behaves as in Standby mode, with the addition that a go-to-sleep
command is issued to the transceiver. The transceiver will remain in Go-to-Sleep mode for
the minimum hold time (t_h(min)) before entering Sleep mode. The transceiver will not enter
Sleep mode if the state of pin STB_N or pin EN is changed or if the Wake flag is set
before t_h(min) has elapsed.
7.1.5 Sleep mode
Sleep mode is the TJA1043’s second-level power saving mode. Sleep mode is entered
via Go-to-Sleep mode, and also when the undervoltage detection time on either V_CC or
V_IO elapses before the relevant voltage level has recovered. In Sleep mode, the
transceiver behaves as described for Standby mode, with the exception that pin INH is set
floating. Voltage regulators controlled by this pin will be switched off, and the current into
pin V_BAT will be reduced to a minimum. Pins STB_N, EN and the Wake flag can be used to
wake up a node from Sleep mode (see Table 4).
7.2 Internal flags
The TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and
system diagnosis support. Five of these flags can be polled by the controller via pin
ERR_N. Which flag is available on pin ERR_N at any time depends on the active
operating mode and on a number of other conditions. Table 5 describes how to access
these flags.
Table 5.
Internal
flag
UV_NOM
UV_BAT
Pwon
Wake
Accessing internal flags via pin ERR_N
Flag is available on pin ERR_N^[1]
Flag is cleared
no
by setting the Pwon or Wake flags, by a
LOW-to-HIGH transition on STB_N or
when both V_IO and V_BAT have
recovered.
no
when V_BAT has recovered
in Listen-only mode (coming from Standby on entering Normal mode
mode, Go-to-Sleep mode, or Sleep mode)
in Standby mode, Go-to-Sleep mode, and on entering Normal mode or by setting
Sleep mode (provided that V_IO and V_BAT the UV_NOM flag
are present)
TJA1043
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 April 2013
© NXP B.V. 2013. All rights reserved.
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