TDA8012AM Datasheet, PDF (7/16 Pages) NXP Semiconductors – Low power PLL FM demodulator for satellite TV receivers

Philips Semiconductors
Low power PLL FM demodulator for
satellite TV receivers
Product specification
TDA8012AM
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Automatic gain control (note 12)
TH_AGC
automatic gain control threshold as a
function of the voltage applied to pin 10
note 13
LD
S_AGC
V_sat(AGC)
level detector
shift
drift
automatic gain control steepness
low level automatic gain control output
saturation voltage
I_AGCO = 0.5 mA;
−
V₁₀ = 0.1V_CC
I_AGCO = 0.5 mA;
61
V₁₀ = 0.9V_CC
V_th(AGC) (pin 10) not
−
connected
V_CC = 4.75 to 5.25 V
−
T_amb = −10 to +80 °C
−
I_AGCO = 0.5 mA; note 14 −
I_AGCO = 1 mA
−
−
53
dBµV
−
−
dBµV
57
−
dBµV
1
−
dB
1
−
dB
8
−
mA/dB
200 500 mV
Keying pulse
t_key
t_W(key)
V_IL
V_IH
Z_i
input keyed pulse time period
keyed pulse width
LOW level input keyed pulse voltage
HIGH level input keyed pulse voltage
input impedance
AFC and carrier detector output (note 15)
I_L(pd)
∆_{-----V-∆---A-f--F---C-}
peak detector leakage current
automatic frequency control steepness
with unmodulated input signal
key on
key off
note 16
−
64
8
−
−
−
3.0
−
1
10
−
µs
−
µs
0.8
V
−
V
−
kΩ
50
150 250 nA
4.5
5.5
6.5
V/MHz
∆f_AFC(shift)
shift of automatic frequency control
voltage with respect to f_VCO with
unmodulated 480 MHz input signal
∆V_CC = ±5%
−
±180 ±500 kHz
∆f_AFC(_drift) drift of automatic frequency control
voltage with respect to f_VCO
T_amb = 80 °C; note 17 −
−1.1 −
MHz
Notes
1. The DC supply current is measured with V_CC = 5 V.
2. The VCO frequency drift is defined as the change in oscillator frequency for a variation of ambient temperature, on
the one hand from T_amb = 25 °C to T_amb = 0 °C and on the other hand from T_amb = 25 °C to T_amb = 50 °C. It is
measured in the application of Fig.4 with the following component values for the tank circuit:
Coil: 2.5 turns; diameter 2 mm; adjustable.
Capacitor: miniature ceramic plate capacitor NP0, 3.3 pF.
3. The circuit is designed for an input level of 57 dBµV. The maximum allowable input level for the PLL design is
61 dBµV. However, for levels different from 57 dBµV, the optimum loop filter values will be different from those given
for the 57 dBµV input level in the reference measuring set-up.
4. The input impedance is reduced to a resistor with a parallel reactance. The values are given at 480 MHz. In order to
reduce the radiation from the oscillator to the RF input, it is recommended to use a symmetrical drive.
5. The PLL loop gain shift and drift are given without loop filter shift and drift (non-temperature compensated external
components).
1997 May 26
7