TDA10085HT Datasheet, PDF (7/16 Pages) NXP Semiconductors – Single chip DVB-S/DSS channel receiver

Philips Semiconductors
Single chip DVB-S/DSS channel receiver
Product specification
TDA10085HT
SYMBOL
PIN
TYPE
DESCRIPTION
TDO
ADVD
ADVS
VDDE
VSSE
CLB#
PSYNC
UNCOR
DEN
OCLK
DO0
DO1
DO2
DO3
VDDI
VSSI
VDDE
VSSE
DO4
DO5
DO6
DO7
22K
VSSI
41
I/O
boundary scan mode: test data serial output; output provided on the
falling edge of TCK
serial mode enabled (ENSERI = 1): serial TS enable input; must be
set to VSS when not in serial mode
42
supply analog supply voltage for the 2nd PLL (typically 1.8 V)
43
ground analog ground voltage for the 2nd PLL
44
supply digital supply voltage (typically 3.3 V)
45
ground digital ground voltage; see note 2
46
I
asynchronous, active LOW input that clears the TDA10085; when
CLB# goes LOW the circuit immediately enters its RESET mode and
normal operation resumes three XIN rising edges later after CLB#
returns HIGH; at RESET, the I²C-bus register contents are all
initialized to their default values; the minimum width of CLB# LOW
level is three XIN clock periods; pin CLB# is not TTL, 5 V tolerant
47
O
packet sync output signal goes HIGH on a rising edge of OCLK each
time the first byte of a packet is provided
48
O
uncorrectable packet output signal goes HIGH on a rising edge of
OCLK when the packet provided is uncorrectable
49
O
data enable; this output signal is HIGH when there is valid data on
bus DO[7:0]
50
O
output clock for the parallel DO[7:0] outputs; OCLK is generated
internally and depends on which interface type is selected
51
O
transport stream data output bits; part of the 8-bit parallel data output
52
O
after demodulation, Viterbi decoding, de-interleaving, RS decoding
53
O
and de-scrambling; possible output interfaces are three parallel and
two serial
54
O
55
supply digital core supply voltage (typically 1.8 V)
56
ground digital core ground voltage; see note 2
57
supply digital supply voltage (typically 3.3 V)
58
ground digital ground voltage; see note 2
59
O
transport stream data output bits; part of the 8-bit parallel data output
60
O
after demodulation, Viterbi decoding, de-interleaving, RS decoding
61
O
and de-scrambling; possible output interfaces are three parallel and
two serial
62
O
63
O
22 kHz output used to control the antenna LNB (output is controlled
via the I²C-bus interface)
64
ground digital core ground voltage; see note 2
Notes
1. TTL, 5 V tolerant input (if VDDE5 is connected to 5 V).
2. DGND, VSSI and VSSE can be connected to the same ground plane.
2001 Aug 31
7