SAA4960 Datasheet, PDF (7/24 Pages) NXP Semiconductors – Integrated PAL comb filter

Philips Semiconductors
Integrated PAL comb filter
Preliminary specification
SAA4960
Internal functional description
SWITCHED CAPACITOR DELAY LINE
Delays the CVBS input signal by 2 lines and 4 lines. Input
signals for the delay lines are the CVBS signal, the clock
CL3 (3 × f_sc), the control signal HSEL and the standard
selection signal SYSPAL.
Output signals are the non-delayed, the 2-line delayed and
the 4-line delayed CVBS signal.
SWITCHED CAPACITOR BAND-PASS FILTERS (BPF)
The comb filter input BPFs attenuate the low frequencies
to guarantee a correct signal processing within the logical
comb filter.
The comb filter output BPF reduces the alias components
that are the result of the non-linear signal processing within
the logical comb filter.
LOGICAL COMB FILTER
Separates the chrominance from the band-pass filtered
CVBS signal.
COMPENSATION DELAY
Compensates the internal processing time of the
band-pass filters and the logical comb filter section.
ADDER
The comb filtered luminance output signal is obtained by
adding the delayed CVBS signal and the inverted comb
filtered chrominance signal.
LOW-PASS FILTER INPUT (LPFI)
Analog input low-pass filter to reduce the outband
frequencies of EMC. The input low-pass filter is included in
the signal path but it can be switched off via the input
signal LPFION.
LOW-PASS FILTER OUTPUT (LPFO1 AND LPFO2)
Two different types of output low-pass filters (LPFO1 and
LPFO2) are necessary to get equal signal delays within the
luminance path and the chrominance path (important for
good transient behaviour). The low-pass output filter type
LPFO1 is used for the luminance output while LPFO2 is
used for the chrominance output. The filters are analog 3^rd
order elliptic low-pass filters that convert the output signals
from the time discrete to the time continuous domain
(reconstruction filter).
LPF CONTROL
Automatic tuning of the low-pass filters is achieved by
adjusting the filter delays. The control information for all
filters (CONT1 and CONT2) is derived from a built-in
reference filter (LPFO1-type) that is part of a control loop.
The control loop tunes the reference filter delay and thus
all other filter delays to a time constant derived from the
system clock CL3.
CONTROL AND CLOCK PROCESSING (CLOCK CONTROL)
The control and clock processing block (see Fig.7)
consists of the sub-blocks PLL, the clock processing and
the mode control. The PLL and the clock processing are
released for operation if the input level at BYP selects the
COMB-mode.
Main tasks of the control and clock processing are:
• Clock generation of system clock CL3
• Delay line start control
• Mode control.
The signal processing is based on a 3 × f_sc system clock
(CL3), that is generated by the clock processing from the
f_sc signal at FSC (pin 1) via a PLL. Because the subcarrier
frequency divided by the line frequency results not in an
integer value a clock phase correction of 180° is necessary
every second line for PAL standards. The clock phase
correction is controlled by the input signals horizontal
sync. Additionally the delay line start is synchronized once
a field to the input signals horizontal sync. The 25 Hz PAL
offset is corrected in this way.
The PLL provides a master clock MCK of 6 × f_sc, which is
locked to the subcarrier frequency at FSC (pin 1).
The system clock CL3 (3 × f_sc) is obtained from MCK by a
divide-by-two circuit. The 180° phase shift is generated by
stopping the divide-by-two circuit for one MCK clock cycle.
The generated clock is a pseudo-line-locked clock that is
referenced to f_sc. The sync separator generates the
necessary signals H_DET and V_DET indicating the line (H)
and the field (V) sync periods.
The current mode of operation (BYPASS or COMB) is
external readable via COMBENA (pin 25).
1996 Oct 15
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