SA5204A Datasheet, PDF (7/13 Pages) NXP Semiconductors – Wide-band high-frequency amplifier

Philips Semiconductors
Wide-band high-frequency amplifier
Product specification
SA5204A
THEORY OF OPERATION
The design is based on the use of multiple feedback loops to
provide wide-band gain together with good noise figure and terminal
impedance matches. Referring to the circuit schematic in Figure 17,
the gain is set primarily by the equation:
V_OUT
V_IN
+ (R_F1 ) R_E1) ń R_E1
(1)
which is series-shunt feedback. There is also shunt-series feedback
due to R_F2 and R_E2 which aids in producing wide-band terminal
impedances without the need for low value input shunting resistors
that would degrade the noise figure. For optimum noise
performance, R_E1 and the base resistance of Q₁ are kept as low as
possible, while R_F2 is maximized.
The noise figure is given by the following equation:
ȡ _{ƪ ƫ}ȣ _rb
)
R_E1
)
KT
2ql_C1
ȧȢ ȧȤ ^{NF + 10Log 1 )}
R_O
dB
(2)
where I_C1=5.5mA, R_E1=12Ω, r_b=130Ω, KT/q=26mV at 25°C and
R₀=50 for a 50Ω system and 75 for a 75Ω system.
The DC input voltage level V_IN can be determined by the equation:
V_IN=V_BE1+(I_C1+I_C3) R_E1(3)
where R_E1=12Ω, V_BE=0.8V, I_C1=5mA and I_C3=7mA (currents rated
at V_CC=6V).
Under the above conditions, V_IN is approximately equal to 1V.
Level shifting is achieved by emitter-follower Q₃ and diode Q₄,
which provide shunt feedback to the emitter of Q₁ via R_F1. The use
of an emitter-follower buffer in this feedback loop essentially
V_CC
eliminates problems of shunt-feedback loading on the output. The
value of R_F1=140Ω is chosen to give the desired nominal gain. The
DC output voltage V_OUT can be determined by:
V_OUT=V_CC–(I_C2+I_C6)R2,(4)
where V_CC=6V, R₂=225Ω, I_C2=8mA and I_C6=5mA.
From here, it can be seen that the output voltage is approximately
3.1V to give relatively equal positive and negative output swings.
Diode Q₅ is included for bias purposes to allow direct coupling of
R_F2 to the base of Q₁. The dual feedback loops stabilize the DC
operating point of the amplifier.
The output stage is a Darlington pair (Q₆ and Q₂) which increases
the DC bias voltage on the input stage (Q₁) to a more desirable
value, and also increases the feedback loop gain. Resistor R₀
optimizes the output VSWR (Voltage Standing Wave Ratio).
Inductors L₁ and L₂ are bondwire and lead inductances which are
roughly 3nH. These improve the high-frequency impedance
matches at input and output by partially resonating with 0.5pF of pad
and package capacitance.
POWER DISSIPATION CONSIDERATIONS
When using the part at elevated temperature, the engineer should
consider the power dissipation capabilities.
At the nominal supply voltage of 6V, the typical supply current is
25mA (32mA max). For operation at supply voltages other than 6V,
see Figure 3 for I_CC versus V_CC curves. The supply current is
inversely proportional to temperature and varies no more than 1mA
between 25°C and either temperature extreme. The change is 0.1%
per °C over the range.
The recommended operating temperature ranges are air-mount
specifications. Better heat-sinking benefits can be realized by
mounting the SO package body against the PC board plane.
1997 Nov 07
V_IN
L1
3nH
R1
650
Q3
Q1
Q4
RF1
140
RE1
12
RF2
200
R2
225 ^R0
L2
10 3nH
V_OUT
Q6
Q2
R3
140
RE2
12
Q5
Figure 17. Schematic Diagram
7
SR00209