PCA9560 Datasheet, PDF (7/17 Pages) NXP Semiconductors – Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch

Philips Semiconductors
Dual 5-bit multiplexed 1-bit latched
I²C EEPROM DIP switch
Product data
PCA9560
CHARACTERISTICS OF THE I²C-BUS
The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as control signals (see Figure 5).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
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Figure 5. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined
as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the
devices which are controlled by the master are the ‘slaves’ (see Figure 7).
SDA
SDA
SCL
S
SCL
P
START condition
STOP condition
Figure 6. Definition of start and stop conditions
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SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
Figure 7. System configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
I²C
MULTIPLEXER
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2003 Jun 27
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