ISP1181 Datasheet, PDF (7/69 Pages) NXP Semiconductors – Full-speed Universal Serial Bus interface device

Philips Semiconductors
ISP1181
Full-speed USB interface
Table 2: Pin description for TSSOP48
Symbol ^[1]
Pin Type Description
ALE
42 I
address latch enable input; a HIGH-to-LOW transition latches
the level on pin AD0 as address information in a multiplexed
address/data bus configuration; must be tied LOW (connect
to DGND) for a separate address/data bus configuration
CS
43 I
chip select input
RESET
44 I
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset; connect to V_CC for power-on reset
(internal POR circuit)
CLKOUT
45 O
programmable clock output (2 mA)
GND
46 -
ground supply
XTAL2
47 O
crystal oscillator output (6 MHz); connect a fundamental
parallel-resonant crystal; leave this pin open when using an
external clock source on pin XTAL1
XTAL1
48 I
crystal oscillator input (6 MHz); connect a fundamental
parallel-resonant crystal or an external clock source (leaving
pin XTAL2 is unconnected)
[1] Symbol names with an overscore (e.g. NAME) represent active LOW signals.
7. Functional description
The ISP1181 is a full-speed USB interface device with up to 14 configurable
endpoints. It has a fast general-purpose parallel interface for communication with
many types of microcontrollers or microprocessors. It supports different bus
configurations (see Table 3) and local DMA transfers of up to 16 bytes per cycle. The
block diagram is given in Figure 1.
The ISP1181 has 2462 bytes of internal FIFO memory, which is shared among the
enabled USB endpoints. The type and FIFO size of each endpoint can be individually
configured, depending on the required packet size. Isochronous and bulk endpoints
are double-buffered for increased data throughput. Interrupt IN endpoints can be
configured in rate-feedback mode.
The ISP1181 requires a single supply voltage of 3.0 to 5.5 V and has an internal
3.3 V voltage regulator for powering the analog USB transceiver. It supports
bus-powered operation.
The ISP1181 operates on a 6 MHz oscillator frequency. A programmable clock output
is available up to 48 MHz. During ‘suspend’ state the 24 kHz LazyClock frequency
can be output.
7.1 Analog transceiver
The transceiver is compliant with Universal Serial Bus Specification Rev. 1.1. It
interfaces directly with the USB cable through external termination resistors.
9397 750 06896
Objective specification
Rev. 01 — 13 March 2000
© Philips Electronics N.V. 2000. All rights reserved.
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