HEF4755V Datasheet, PDF (7/12 Pages) NXP Semiconductors – Transceiver for serial data communication

Philips Semiconductors
Transceiver for serial data communication
Product specification
HEF4755V
LSI
Redundancy byte
The redundancy byte completes the data bytes with 15 (7)
bits as a code word. If only one bit in the information has
changed during the transmission, the two code words will
differ by at least 6 (4) bit positions. So a change of up to 5
(3) bits will always be observed, even every odd number of
false bits will be recognized. The HEF4755V has a
programmable redundancy bit calculator which carries out
this protection (the numbers given in parentheses are valid
for the alternative possibility).
If the transmission line carries extreme noise, this kind of
message protection is less effective. In this case, the
message is protected by checking bit-per-bit in a smaller
time scale (see ‘bit protection’ below).
Bit protection
The HEF4755V checks every received bit within the time
window defined by the start-bit. The programmed time
tolerance (19%, 25%, 31% and 37%) determines that the
bit protection circuit decides after 32 samples which bit is
a true logic HIGH or LOW level, or an error. In the latter
case, there are too many samples HIGH to obtain a LOW
and, too many samples LOW to obtain a HIGH.
Transmitting
In the transmitting mode the HEF4755V uses the data
pulse signal (DP, pin 23) to take 8 bits from the data bus.
These parallel bits are shifted serially to the message
output (MO).
Receiving
In the receiving mode the HEF4755V receives serial bits at
the message input (MI). The circuit checks the message
for transmission errors and, with every data pulse, 8 bits
are transferred in parallel to the data bus. Every
recognized error is stored and the error output is activated.
The kind of error can be recognized by reading the status
register over the data bus.
Asynchronous and synchronous mode
If only one transmission line is available, then the receiver
waits for the start-bit, synchronizes itself on the start bit
and receives all the data bits of one message. This is
called the asynchronous mode. By using 3 transmission
lines, the circuit can go to the synchronous mode. In this
case it is possible to transmit also the clock signal (CP)
and message synchronization signal (MOS) in parallel with
the data bits. The start bit and the bit check are omitted. In
the synchronous mode the maximum transmission speed
is 32 times the maximum speed in the asynchronous
mode.
In asynchronous receive mode a reset pulse is necessary
between two messages. It is possible to derive this reset
pulse from the busy signal by using hardware. The
duration of the START-pulse at the transmitter must
always be shorter than the message to be transferred. A
good procedure for achieving this is to use the
BUSY-signal to end the START-pulse. The recovery time
between two messages must be at least two bit periods.
During this time, the line must remain stable to prevent
generation of an error. This must be ensured with external
hardware/software.
In the synchronous receive mode, the duration of the
START-pulse at the transmitter must always be shorter
than the message to be transferred. A good procedure for
achieving this is to use the BUSY-signal to end the
START-pulse. A continuous START-signal will cause
malfunction. The recovery time between two messages
must be at least one bit period. During this time, the
message line must remain stable. A good way to achieve
this is to use the trailing-edge of the BUSY-signal to
generate a START-signal. In practice, if data is delivered
to the transmitter fast enough, START can be BUSY. If the
lines have different delays, the message line should have
the longest delay. If it is not certain which line has the
longest delay it is possible to phase-shift the clock signal
of the receiver by inverting it. This is only possible with
point-to-point lines.
January 1995
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