HEF40195B Datasheet, PDF (7/8 Pages) NXP Semiconductors – 4-bit universal shift register

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Dynamic power
dissipation per
package (P)
V_DD
V
TYPICAL FORMULA FOR P (µW)
5
1900 f_i + ∑ (f_oC_L) × V_DD2
10
8300 f_i + ∑ (f_oC_L) × V_DD2
15
22 800 f_i + ∑ (f_oC_L) × V_DD2
where
f_i = input freq. (MHz)
f_o = output freq. (MHz)
C_L = load capacitance (pF)
∑ (f_oC_L) = sum of outputs
V_DD = supply voltage (V)
Fig.4 Waveforms showing set-up times, hold times for J, K and P_n inputs; minimum MR pulse width, MR to output delays and MR to CP
recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be specified
as negative values.