 English |
|
|
|
|
|
|
|
| HEF4014BT653 Datasheet, PDF (7/14 Pages) NXP Semiconductors – 8-bit static shift register | |||
| |||
| ◁ |
NXP Semiconductors
HEF4014B
8-bit static shift register
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ï£ 20 ns; Tamb = 25 ï°C.
Symbol Parameter
VDD
Typical formula for PD (ïW)
Where:
PD
dynamic power 5 V
PD = 900 ï´ fi + ï(fo ï´ CL) ï´ VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 4300 ï´ fi + ï(fo ï´ CL) ï´ VDD2
fo = output frequency in MHz;
15 V
PD = 12000ï ï´ fi + ï(fo ï´ CL) ï´ VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
ï(CL ï´ fo) = sum of the outputs.
12. Waveforms
VI
CP input
VSS
VOH
Qn output
VOL
VM
tPHL
90 %
VM
10 %
tt
Measurement points are given in Table 9.
Fig 4. CP to Qn propagation delays and output transition times
tPLH
tt
001aaj456
VI
CP input
VSS
VI
D input
VSS
VI
PE input
VSS
VI
DS input
VSS
50 %
tsu
th
50 % 50 %
tsu
th
50 % 50 %
50 %
tW
50 %
tr
fclk(max)
50 %
tf
tsu
50 %
th
50 %
tsu
th
50 % 50 %
001aae559
Fig 5.
The shaded areas indicate where change is permitted for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 â 21 November 2011
© NXP B.V. 2011. All rights reserved.
7 of 14
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese