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74HC6323A Datasheet, PDF (7/15 Pages) NXP Semiconductors – Programmable ripple counter with oscillator; 3-state | |||
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Philips Semiconductors
Programmable ripple counter with
oscillator; 3-state
Product speciï¬cation
74HC/HCT6323A
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
25
â40 to 85 â40 to 125 UNIT VCC
MIN TYP MAX MIN MAX MIN MAX
(V)
VI
OTHER
tPHL/tPLH
propagation
â
delay X1 to
â
OUT divide by 1 â
61 185 â
22 37 â
19 31 â
230 â
46 â
39 â
275 ns
55 ns
47 ns
2.0 Fig.7 S1 = GND
4.5
S2 = GND
6.0
tPHL/tPLH
propagation
â
delay X1 to
â
OUT divide by 2 â
74 235 â
27 47 â
23 40 â
290 â
58 â
49 â
350 ns
70 ns
60 ns
2.0 Fig.7 S1 = GND
4.5
S2 = VCC
6.0
tPHL/tPLH
propagation
â
delay X1 to
â
OUT divide by 4 â
91 285 â
33 57 â
28 48 â
355 â
71 â
60 â
425 ns
85 ns
72 ns
2.0 Fig.7 S1 = VCC
4.5
S2 = GND
6.0
tPHL/tPLH
propagation
â
delay X1 to
â
OUT divide by 8 â
105 335 â
38 67 â
32 57 â
415 â
83 â
71 â
500 ns
100 ns
85 ns
2.0 Fig.7 S1 = VCC
4.5
S2 = VCC
6.0
tPLZ/tPHZ 3-state output â
disable time
â
MR to OUT
â
75 150 â
15 30 â
13 26 â
185 â
37 â
31 â
225 ns
45 ns
38 ns
2.0 Fig.8
4.5
6.0
tPZL
3-state output â
36 150 â
185 â
225 ns 2.0 Fig.8
enable time
â
13 30 â
37 â
45 ns 4.5
MR to OUT
â
11 26 â
31 â
38 ns 6.0
tPZH
3-state output â
61 200 â
250 â
300 ns 2.0 Fig.8 note 1
enable time
â
22 40 â
50 â
60 ns 4.5
MR to OUT
â
19 34 â
43 â
51 ns 6.0
tTHL/tTLH output
â
transition time â
â
14 60 â
5
12 â
4
10 â
75 â
15 â
13 â
90 ns
19 ns
15 ns
2.0 Fig.7
4.5
6.0
tW
clock pulse
50 17 â
60 â
75 â
ns 2.0 Fig.7
width X1,
10 6.0 â
12 â
15 â
ns 4.5
HIGH or LOW 9
5
â
10 â
13 â
ns 6.0
tW
master reset
80 22 â
100 â
120 â
ns 2.0 Fig.9
pulse width
16 8
â
20 â
24 â
ns 4.5
MR; LOW
14 7
â
17 â
20 â
ns 6.0
trem
removal time 100 19 â
125 â
150 â
ns 2.0 Fig.9
MR to X1
20 7
â
25 â
30 â
ns 4.5
17 6.0 â
21 â
26 â
ns 6.0
fmax
maximum clock 10 17 â
8
â
6.6 â
MHz 2.0 Fig.7
pulse frequency 50 85 â
40 â
33 â
MHz 4.5
59 100 â
47 â
39 â
MHz 6.0
Note to the 74HC AC Characteristics
1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
September 1993
7
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