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74HC4024 Datasheet, PDF (7/7 Pages) NXP Semiconductors – 7-stage binary ripple counter
Philips Semiconductors
7-stage binary ripple counter
AC WAVEFORMS
Product specification
74HC/HCT4024
Also showing the master reset (MR) pulse width, the
master reset to output (Qn) propagation delays and the
master reset to clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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