74HC4020 Datasheet, PDF (7/7 Pages) NXP Semiconductors – 14-stage binary ripple counter

Philips Semiconductors
14-stage binary ripple counter
AC WAVEFORMS
Product specification
74HC/HCT4020
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.7 Waveforms showing the clock (CP) to output (Q_n) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q_n) propagation delays
and the master reset to clock (CP) removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
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