|
TDA8351AQ Datasheet, PDF (6/16 Pages) NXP Semiconductors – DC-coupled vertical deflection output circuit | |||
|
◁ |
Philips Semiconductors
DC-coupled vertical deï¬ection output
circuit
Product speciï¬cation
TDA8351AQ
CHARACTERISTICS
VP = 17.5 V; VFB = 45 V; fi = 50 Hz; II(sb) = 400 µA; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise
speciï¬ed.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
DC supply
VP
operating supply voltage
VFB
ï¬yback supply voltage
IP
supply current
9.0
VP
note 1
VP
no signal; no load
â
Vertical circuit
VO
LE
VO
VDF
|Ios|
|Vos|
âVosT
output voltage swing (scan)
linearity error
output voltage swing (ï¬yback)
VO(A) â VO(B)
forward voltage of the internal
efï¬ciency diode (VO(A) â VFB)
output offset current
offset voltage at the input of the
feedback ampliï¬er (VI(fb) â VO(B))
output offset voltage as a function
of temperature
Idiff = 0.6 mA (p-p);
Vdiff = 1.8 V (p-p);
IO = 3 A (p-p)
IO = 3 A (p-p); note 2
IO = 50 mA (p-p); note 2
Idiff = 0.3 mA;
IO = 1.5 A
IO = â1.5 A;
Idiff = 0.3 mA
Idiff = 0;
II(sb) = 50 to 500 µA
Idiff = 0;
II(sb) = 50 to 500 µA
Idiff = 0
19.8
â
â
â
â
â
â
â
VO(A)
DC output voltage
Idiff = 0; note 3
â
Gvo
open-loop voltage gain (V9-5/V1-2) notes 4 and 5
â
open loop voltage gain
note 4
â
(V9-5/V3-5; V1-2 = 0)
VR
voltage ratio V1-2/V3-5
â
fres
frequency response (â3 dB)
open loop; note 6
â
GI
current gain (IO/Idiff)
â
âGcT
current gain drift as a function of
â
temperature
II(sb)
IFB
PSRR
VI(DC)
VI(CM)
Ibias
IO(CM)
signal bias current
ï¬yback supply current
power supply ripple rejection
DC input voltage
common mode input voltage
input bias current
common mode output current
50
during scan
â
note 7
â
â
II(sb) = 0
0
II(sb) = 0
â
âII(sb) = 300 µA (p-p); â
fi = 50 Hz; Idiff = 0
â
25
â
50
â
60
30
55
â
â
1
3
1
3
39
â
â
1.5
â
30
â
18
â
72
8.0
â
80
â
80
â
0
40
5 000
â
â
â
â
10â4
400
500
â
100
80
â
2.7
â
â
1.6
0.1
0.5
0.2
â
V
V
V
mA
V
%
%
V
V
mA
mV
µV/K
V
dB
dB
dB
Hz
K
µA
µA
dB
V
V
µA
mA
1999 Sep 27
6
|
▷ |