TDA4663T Datasheet, PDF (6/12 Pages) NXP Semiconductors – Baseband delay line

Philips Semiconductors
Baseband delay line
Product specification
TDA4663T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
α_{ct(16, 11)}
SVRR
V_{11, 12(p-p)}
V_{11, 12(p-p)}
t_d
crosstalk direct from input to output V₁₄ = 0 V; R_S = 300 Ω; 30
−
−
dB
signal
V₁₆ = 1.35 V (p-p)
supply voltage ripple rejection
V_R = 100 mV (p-p); 34
−
−
dB
∆V_{11, 12}/V_R
f_R = 10 Hz to 1 kHz;
V_{11, 12} = 1.35 V (p-p)
clamping offset during H-clamp
V₁₄ = V₁₆ = 0 V;
−
−
5
mV
(peak-to-peak value)
R_S = 300 Ω
unwanted signals (line-locked)
V₁₄ = V₁₆ = 0 V;
(peak-to-peak value)
active video;
residual clock (3 MHz)
R_S = 300 Ω
−
−
6.25
mV
meander
−
−
1.5
mV
needles
−
−
2.5
mV
line delay time
for PAL signals
64 − 0.125 64 − 0.055 64 + 0.015 µs
for NTSC signals
63.555 − 63.555 − 63.555 + µs
0.125
0.055
0.015
Sandcastle pulse input (pin 5)
f_BK
V₅
t_BK
V_slice
I_i
C_i
t_li
burst-key frequency/sandcastle
frequency
top pulse voltage
top pulse duration
internal slicing level
input current
input capacitance
lock-in time for PLL
note 2
14.2
15.625
4.0
−
−
2.5
V₅ − 1.0 −
−
−
−
−
−
−
17.0
kHz
V_P + 1.0 V
−
µs
V₅ − 0.5 V
10
µA
10
pF
1
ms
Clamping pulse input (pin 7)
V_clamp
I_i
C_i
t_clamp
t_r
t_f
clamping pulse ON
clamping pulse OFF
input current
input capacitance
clamping pulse duration
rise time
fall time
3.5
V_P − 0.1 V_P
V
−0.5
+0.1
+1.5
V
−
−
10
µA
−
−
10
pF
0.1
2
3
µs
10
−
−
ns
10
−
−
ns
Notes
1. Noise voltage at f = 10 kHz to 1 MHz; R_S < 300 Ω.
2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing.
1996 Nov 22
6