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| PSMN2R8-25MLC_15 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using | |||
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NXP Semiconductors
PSMN2R8-25MLC
N-channel 25 V 2.8 m⦠logic level MOSFET in LFPAK33 using NextPower Technology
Table 6. Characteristics â¦continued
Symbol
Parameter
Conditions
td(on)
tr
td(off)
tf
Qoss
turn-on delay time
rise time
turn-off delay time
fall time
output charge
Source-drain diode
VDS = 12.5 V; RL = 0.5 â¦; VGS = 4.5 V;
RG(ext) = 5 â¦
VGS = 0 V; VDS = 12.5 V; f = 1 MHz;
Tj = 25 °C
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 15
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 12.5 V
ta
reverse recovery rise VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
time
VDS = 12.5 V; see Figure 16
tb
reverse recovery fall
time
Min Typ Max Unit
-
16.4 -
ns
-
24.6 -
ns
-
19.9 -
ns
-
13.1 -
ns
-
14.3 -
nC
-
0.82 1.1 V
-
21.3 -
ns
-
14.1 -
nC
-
12.1 -
ns
-
9.2 -
ns
75
ID 10 4.5
(A)
3.5
60
003aaj766
3
45
2.8
30
15
2.6
VGS (V) = 2.4
0
0
0.5
1
1.5
2
VDS(V)
20
RDSon
(mΩ)
15
003aaj767
10
5
0
0
4
8
12
16
VGS (V)
Fig 6. Output characteristics; drain current as a
Fig 7. Drain-source on-state resistance as a function
function of drain-source voltage; typical values
of gate-source voltage; typical values
PSMN2R8-25MLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 â 15 June 2012
© NXP B.V. 2012. All rights reserved.
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