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| PSMN0R7-25YLD_15 Datasheet, PDF (6/10 Pages) NXP Semiconductors – N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology | |||
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NXP Semiconductors
PSMN0R7-25YLD
N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
td(on)
tr
turn-on delay time
rise time
VDS = 12 V; RL = 0.4 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf
fall time
Qoss
output charge
VGS = 0 V; VDS = 12 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 12 V; Fig. 5
[1]
ta
reverse recovery rise
time
tb
reverse recovery fall
time
S
softness factor
Min Typ Max Unit
-
[tbd] -
ns
-
[tbd] -
ns
-
[tbd] -
ns
-
[tbd] -
ns
-
58.5 -
nC
-
0.78 1.2 V
-
[tbd] -
ns
-
[tbd] -
nC
-
[tbd] -
ns
-
[tbd] -
ns
-
[tbd] -
[1] includes capacitive recovery
VDS
ID
VGS(pl)
VGS(th)
VGS
QGS1 QGS2
QGS
QGD
QG(tot)
003aaa508
Fig. 4. Gate charge waveform definitions
003aal160
ID
(A)
trr
ta
tb
0
0.25 IRM
IRM
t (s)
Fig. 5. Reverse recovery timing definition
PSMN0R7-25YLD
Objective data sheet
All information provided in this document is subject to legal disclaimers.
15 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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