PHP7N40E Datasheet, PDF (6/9 Pages) NXP Semiconductors – PowerMOS transistors Avalanche energy rated

Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHP7N40E, PHB7N40E
15 ^{VGS, Gate-Source voltage (Volts)}
ID = 7.2 A
Tj = 25 C
240 V
PHP5N40
80 V
VDD = 320 V
10
5
0
0
10 20 30 40 50 60 70 80
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
1000 ^{Switching times (ns)}
VDD = 200 V
VGS = 10 V
RD = 27 Ohms
Tj = 25 C
PHP5N40
100 _td(off)
tf
tr
td(on)
10
0
10
20
30
40
50
60
RG, Gate resistance (Ohms)
Fig.14. Typical switching times; t_d(on), t_r, t_d(off), t_f = f(R_G)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage;
V_(BR)DSS/V_{(BR)DSS 25 ˚C} = f(T_j)
20 ^{IF, Source-Drain diode current (Amps)}
VGS = 0 V
15
PHP5N40
10
150 C
Tj = 25 C
5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4
VSDS, Source-Drain voltage (Volts)
Fig.16. Source-Drain diode characteristic.
I_F = f(V_SDS); parameter T_j
Non-repetitive Avalanche current, IAS (A)
10
25 C
Tj prior to avalanche = 125 C
1
VDS
ID
0.1
1E-06
tp
PHP7N40E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.17. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_p);
unclamped inductive load
Maximum Repetitive Avalanche Current, IAR (A)
10
Tj prior to avalanche = 25 C
125 C
1
0.1
0.01
1E-06
PHP7N40E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.18. Maximum permissible repetitive avalanche
current (I_AR) versus avalanche time (t_p)
December 1998
6
Rev 1.200