PESD5V0U2BM Datasheet, PDF (6/11 Pages) NXP Semiconductors – Ultra low capacitance bidirectional double ESD protection array

NXP Semiconductors
PESD5V0U2BM
Ultra low capacitance bidirectional double ESD protection array
7. Application information
The PESD5V0U2BM is designed for the protection of up to two bidirectional data or signal
lines from the damage caused by ESD and surge pulses. The device may be used on
lines where the signal polarities are both, positive and negative with respect to ground.
signal lines
DUT
GND
006aab332
Fig 5. Application diagram
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the PESD5V0U2BM as close to the input terminal or connector as possible.
2. The path length between the PESD5V0U2BM and the protected line should be
minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
PESD5V0U2BM_1
Product data sheet
Rev. 01 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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