PCF2104X Datasheet, PDF (6/56 Pages) Motorola, Inc – LCD controller/driver

Philips Semiconductors
LCD controller/driver
Product specification
PCF2104x
7.8 OSC: oscillator
When the on-chip oscillator is used, this pin must be
connected to V_DD. An external clock signal, if used, is input
at this pin.
8.2 Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to V_DD.
7.9 SCL: serial clock line
Input for the I²C-bus clock signal.
7.10 SDA: serial data line
Input/output for the I²C-bus data line.
7.11 SA0: address pin
The hardware sub-address line is used to program the
device sub-address for 2 different PCF2104xs on the
same I²C-bus.
7.12 T1: test pad
Must be connected to V_SS. Not user accessible.
8 FUNCTIONAL DESCRIPTION (see Fig.1)
8.1 LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.
The optimum value of V_OP depends on the multiplex rate,
the LCD threshold voltage (V_th) and the number of bias
levels. The relationships are given in Table 1.
Using a 5-level bias scheme for 1 : 16 MUX rate allows
V_OP < 5 V for most LCD liquids. The effect on the display
contrast is negligible.
Table 1 Optimum values for V_OP
MUX
RATE
NUMBER
OF BIAS
LEVELS
V_OP/V_th
DISCRIMINATION
V_on/V_off
1 : 16
5
3.67
1 : 32
6
5.19
1.277
1.196
8.3 External clock
If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
f_frame = ¹â„₂₃₀₄f_osc. A clock signal must always be present,
otherwise the LCD may be frozen in a DC state.
8.4 Power-on reset
The Power-on reset block initializes the chip after
power-on or power failure.
8.5 Registers
The PCF2104x has two 8-bit registers, an instruction
register (IR) and a data register (DR). The register select
signal (RS) determines which register will be accessed.
The instruction register stores instruction codes such as
display clear and cursor shift, and address information for
the Display Data RAM (DDRAM) and Character Generator
RAM (CGRAM). The instruction register can be written to,
but not read from, by the system controller.
The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
Address Counter) is written to the data register prior to
being read by the ‘Read data’ instruction.
8.6 Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2104x. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output at pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is at logic 0 or waiting for the required number
of clock cycles.
1997 Dec 16
6