PCA9542 Datasheet, PDF (6/10 Pages) NXP Semiconductors – 2-channel I2C multiplexer and interrupt controller

Philips Semiconductors
2-channel I²C multiplexer and interrupt controller
Product specification
PCA9542
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
S
not acknowledge
acknowledge
1
2
8
9
START condition
Figure 4. Acknowledgement on the I²C-bus
clock pulse for
acknowledgement
slave address
1 1 1 0 A2 A1 A0
fixed
hardware selectable
Figure 5. Slave address
SW00453
SDA
X XX X X X X XX X XX X XXX
SCL
12 34 5 67 89 1234 5 67 89
SLAVE ADDRESS
CONTROL REGISTER
SDA S 1 1 1 0 A2 A1 A0 0 A X X INT1 INT0 X B2 B1 B0 A P
start condition
R/W acknowledge
from slave
acknowledge
from slave
PREVIOUS CHANNEL
Figure 6. WRITE control register
NEW CHANNEL
t_pv
SW00480
SW00368
1999 Oct 07
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA S 1 1 1 0 A2 A1 A0 1 A X X INT1 INT0 X B2 B1 B0 NA P
start condition
R/W acknowledge
from slave
Figure 7. READ control register
no acknowledge
from master
stop condition
SW00481
6