74HC4052 Datasheet, PDF (6/27 Pages) NXP Semiconductors – Dual 4-channel analog multiplexer/demultiplexer

Philips Semiconductors
Dual 4-channel analog multiplexer,
demultiplexer
Product specification
74HC4052; 74HCT4052
handbook, full pagewidth
nYn
VCC
VEE
VCC
VCC
from
logic
VEE
VCC
VEE
nZ
MNB043
Fig.6 Schematic diagram (one switch).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to V_EE = GND
(ground = 0 V); note 1.
SYMBOL
V_CC
I_IK
I_SK
I_S
I_EE
I_CC; I_GND
T_stg
P_tot
P_S
PARAMETER
supply voltage
input diode current
switch diode current
switch current
V_EE current
V_CC or GND current
storage temperature
power dissipation
power dissipation per switch
CONDITIONS
V_I < −0.5 V or V_I > V_CC + 0.5 V
V_S < −0.5 V or V_S > V_CC + 0.5 V
−0.5 V < V_S < V_CC + 0.5 V
T_amb = −40 °C to +125 °C; note
MIN.
−0.5
−
−
−
−
−
−65
−
−
MAX.
+11.0
±20
±20
±25
±20
±50
+150
500
100
UNIT
V
mA
mA
mA
mA
mA
°C
mW
mW
Notes
1. To avoid drawing V_CC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the
bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no V_CC current will flow out of
pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may
not exceed V_CC or V_EE.
2. For DIP16 packages: above 70 °C derate linearly with 12 mW/K.
For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.
2004 Nov 11
6