SAA7724H Datasheet, PDF (59/84 Pages) NXP Semiconductors – Car radio digital signal processor

Philips Semiconductors
Car radio digital signal processor
Preliminary specification
SAA7724H
handbook, full pagewidth _I2C-bus
R(B)DS status
register read
DAVN
t _DAVNL
T _TDAV
MGW229
Fig.33 RDS data available signal (DAVN); DAVN LOW timing shorten by data request via I²C-bus (decoder is
synchronized).
11 I²C-BUS CONTROL
General description of the I²C-bus format in a booklet can
be obtained at Philips Semiconductors, International
Marketing and Sales.
For the external control of the chip a fast I²C-bus is
implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus. There are two
different types of control instructions:
• Instructions to control the DSP programs, programming
the coefficient RAM and reading the values of
parameters
• Instructions controlling the DATA I²S-bus flow, like
source selection and clock speed.
11.1 I²C-bus protocol
The bidirectional I²C-bus interface acts as a slave
transceiver while an external microcontroller acts as a
master transceiver. Communication between the MPI and
the microcontroller is based on the I²C-bus protocol. The
data transfer on the I²C-bus is shown in Fig.34.
The I²C-bus has two lines: a Serial Clock line SCL and a
Serial Data line SDA. Because the I²C-bus is a
multi-master bus, arbitration between different master
devices is achieved by using a START condition. The
master device pulls the open-drain data line LOW while the
clock line remains HIGH. After the bus has been ‘won’ in
this way, data is transmitted serially in packets of 8 bits
plus an extra clock pulse for an acknowledgement flag
from the receiving device.
handbook, full pagewidth
SDA
7
6
0
ACK
SCL
7
6
0
START
data MSB
data 2
data LSB
acknowledge STOP
MGW217
Fig.34 I²C-bus interface data transfer sequence.
2003 Nov 18
59