SAA7146AH-V4.557 Datasheet, PDF (56/139 Pages) NXP Semiconductors – Multimedia bridge, high performance Scaler and PCI circuit

Philips Semiconductors
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Product specification
SAA7146A
handbook, full pagewidth
LLC
HS
VS
FLD
V-DMSD
FLD-DMSD
MHB054
Fig.12 Timing of field detection ODD-to-EVEN for direct mode.
7.8.7 ACQUISITION CONTROL
The processing window for the scaling unit is defined in the acquisition control. The internal counters (one for the HPS
and one for the BRS) receives programmable values for offset (HXO11 to HXO0, HYO11 to HYO0 and BXO9 to BXO0,
BYO9 to BYO0) and length (NumLines, NumBytes). These counters are reset by the corresponding sync reference input
signal. The horizontal counter increments in qualified pixels for the HPS and qualified bytes for the BRS, the vertical
counter increments in qualified lines, i.e. lines containing at least one qualified pixel. In order to avoid programming
dependent line drop effects, the horizontal offset value must not exceed the number of pixels per line. In order to avoid
programming dependent field drop effects, the vertical offset value must not exceed the number of lines per field.
The acquisition provides the possibility to re-program the vertical offset after the previous job is done (EOW at the
HPS and BRS is reached). Thus multiple windows can be opened during one field.
2004 Aug 25
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