ISP1181B Datasheet, PDF (53/70 Pages) NXP Semiconductors – Full-speed Universal Serial Bus peripheral controller

Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
ALE
AD0
t _LH
t _LLAX
t _AVLL
A0
D0
DATA
Fig 20. ALE timing.
MGS790
21.2 Access cycle timing
Table 58: Dynamic characteristics: access cycle timing
Symbol
Parameter
Conditions
Write command + write data (see Figure 21 and Figure 22)
T_cy(WC-WD)
cycle time for write command,
then write data
T_cy(WD-WD)
T_cy(WD-WC)
cycle time for write data
cycle time for write data, then
write command
Write command + read data (see Figure 23 and Figure 24)
T_cy(WC-RD)
cycle time for write command,
then read data
T_cy(RD-RD)
T_cy(RD-WC)
cycle time for read data
cycle time for read data, then
write command
8-bit bus
16-bit bus
Unit
Min
Max
Min
Max
100^[1]
-
205
-
ns
90
-
205
-
ns
90
-
205
-
ns
100^[1]
-
205
-
ns
90
-
205
-
ns
90
-
205
-
ns
[1] Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete.
DATA
WR
command
data
Tcy(WC-WD)
CS
Fig 21. Write command + write data cycle timing.
data
Tcy(WD-WD)
MGT022
9397 750 13958
Product data
Rev. 02 — 07 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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