87LPC769 Datasheet, PDF (52/61 Pages) NXP Semiconductors – Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D, and DAC

Philips Semiconductors
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
Preliminary specification
87LPC769
EPROM Characteristics
Programming of the EPROM on the 87LPC769 is accomplished with
a serial programming method. Commands, addresses, and data are
transmitted to and from the device on two pins after programming
mode is entered. Serial programming allows easy implementation of
in-circuit programming of the 87LPC769 in an application board.
Details of the programming algorithm may be found in a separate
document that is available on the Philips web site at:
http://www.semiconductors.philips.com/mcu/support/progspecs/
The 87LPC769 contains three signature bytes that can be read and
used by an EPROM programming system to identify the device. The
signature bytes designate the device as an 87LPC769 manufactured
by Philips. The signature bytes may be read by the user program at
addresses FC30h, FC31h and FC60h with the MOVC instruction,
using the DPTR register for addressing.
A special user data area is also available for access via the MOVC
instruction at addresses FCE0h through FCFFh. This “customer
code” space is programmed in the same manner as the main code
EPROM and may be used to store a serial number, manufacturing
date, or other application information.
32-Byte Customer Code Space
A small supplemental EPROM space is reserved for use by the
customer in order to identify code revisions, store checksums, add a
serial number to each device, or any other desired use. This area
exists in the code memory space from addresses FCE0h through
FCFFh. Code execution from this space is not supported, but it may
be read as data through the use of the MOVC instruction with the
appropriate addresses. The memory may be programmed at the
same time as the rest of the code memory and UCFG bytes are
programmed.
System Configuration Bytes
A number of user configurable features of the 87LPC769 must be
defined at power up and therefore cannot be set by the program after
start of execution. Those features are configured through the use of
two EPROM bytes that are programmed in the same manner as the
EPROM program space. The contents of the two configuration bytes,
UCFG1 and UCFG2, are shown in Figures 39 and 40. The values of
these bytes may be read by the program through the use of the
MOVX instruction at the addresses shown in the figure.
UCFG1 Address: FD00h
Unprogrammed Value: FFh
7
6
WDTE RPD
5
PRHI
4
BOV
3
2
1
0
CLKR FOSC2 FOSC1 FOSC0
BIT
UCFG1.7
UCFG1.6
UCFG1.5
UCFG1.4
UCFG1.3
SYMBOL
WDTE
RPD
PRHI
BOV
CLKR
UCFG1.2–0 FOSC2–FSOC0
FOSC2–FOSC0
111
011
010
001
000
FUNCTION
Watchdog timer enable. When programmed (0), disables the watchdog timer. The timer may
still be used to generate an interrupt.
Reset pin disable. When 1 disables the reset function of pin P1.5, allowing it to be used as an
input only port pin.
Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state.
This bit should always be programmed to a zero.
Clock rate select. When 0, the CPU clock rate is divided by 2. This results in machine cycles
taking 12 CPU clocks to complete as in the standard 80C51. For full backward compatibility,
this division applies to peripheral timing as well.
CPU oscillator type select. See Oscillator section for additional information. Combinations
other than those shown below should not be used. They are reserved for future use.
Oscillator Configuration
External clock input on X1 (default setting for an unprogrammed part).
Internal RC oscillator, 6 MHz ±25%.
Low frequency crystal, 20 kHz to 100 kHz.
Medium frequency crystal or resonator, 100 kHz to 4 MHz.
High frequency crystal or resonator, 4 MHz to 20 MHz.
Figure 39. EPROM System Configuration Byte 1 (UCFG1)
SU01378
2001 Jan 11
49