PNX8510 Datasheet, PDF (50/92 Pages) NXP Semiconductors – Analog companion chip

Philips Semiconductors
PNX8510/11
Analog companion chip
Table 29: PNX8510/11 video registers…continued
* indicates not present in secondary video channel
Bit Symbol
Access Value Description
7:0 0x63=FSC0
0x64=FSC1
0x65=FSC2
0x66=FSC3
R/W 0x2A0 ffsc: subcarrier frequency (in multiples of line frequency)
98ACB fllc: clock frequency (in multiples of line frequency)
FSC = round ((ffsc/fllc)x2^32)
FSC3 most significant byte
FSC0 least significant byte
NTSC-M: ffsc 227.5, fllc 1716 -> FSC = 21F07C1F
PAL-B/G: ffsc 283.7516, fllc 1728 -> FSC = 2A098ACB
SECAM: ffsc 274.304, fllc 1728 -> FSC = 28A33BB2
Offset 0x67 - L21O0
7:0 L21O0
R/W 0x0 First byte of closed captioning data, odd field
Offset 0x68 - L21O1
7:0 L21O1
R/W 0x0 Second byte of closed captioning data, odd field
Offset 0x69 - L21E0
7:0 L21E0
R/W 0x0 First byte of closed captioning data, even field
Offset 0x6A - L21E1
7:0 L21E1
R/W 0x0 Second byte of closed captioning data, even field
Offset 0x6B - Must be initialized to zero.
Offset 0x6C - TRGCTL1*
7:0 HTRIG
R/W 0x01 Sets horizontal trigger phase related to encoder input.
Values above 1715 (FISE=1) or 1727 (FISE=0) are not allowed.
Increasing HTRIG decreases delay as of all internally generated
timing signals. This register is for the SD path.
Reference mark: analog output horizontal sync (leading slope)
coincides with active edge of RCV used for triggering at
HTRIG=0x398.
Offset 0x6D - TRGCTL2*
7:5 HTRIG
R/W 0x1 Sets horizontal trigger phase related to encoder input.This register
is for the SD path.
4:0 VTRIG
R/W 0x0 Increasing VTRIG decreases delays of all internally generated
timing signals measured in half lines.
Variation range of VTRIG = 0 to 0x1F
Offset 0x6E - MULTICTL
7
Unused
-
6
BLCKON
R/W 0
0 = Encoder in normal operation mode
1 = Output signal is forced to blanking level. This doesn’t shutdown
the sync and leaves it running.
5:4 PHRES
R/W 0x2 Selects the phase reset mode of the color subcarrier.
00 = No phase reset or reset via RTC
01 = Phase reset every two lines
10 = Reset every eight fields
11 = Reset every four fields
9397 750 12612
Product data
Rev. 04 – 12 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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