TDA8735 Datasheet, PDF (5/16 Pages) NXP Semiconductors – PLL frequency synthesizer

Philips Semiconductors
PLL frequency synthesizer
Product specification
TDA8735
Table 1 Divider number setting; note 1
ON
DIVIDER NUMBER SETTING
0
(S0 + S1) × 2¹ to + S13 × 2¹³ + S14 × 2¹⁴
Note
1. Where the minimum divider ratio is: 2⁶ = 64 to 2¹⁵ − 1 = 32761.
INPUT
ON
Table 2 Bit CP (used to control the charge pump;
DB0 : D0)
CP
CURRENT
0
LOW
1
HIGH
Table 3 Bits REF1 and REF2 (used to set the reference
frequency applied to the phase detector;
DB2 : D7 and D6)
REF1
0
0
1
1
REF2
0
1
0
1
FREQUENCY (kHz)
1
10
25
0
Table 4 Bit OPAMP (used to control the switch in the
tuning voltage amplifier output circuitry;
DB2 : D4)
OPAMP
1
0
SWITCH
on
off
Table 5 Bit BS (used to control the open-collector switch
output; DB2 : D2)
BS
SWITCH OUTPUT
1
sink current
0
floating
The data byte DB3 must be set to 0 to 0. It is also used for
test purposes (see Fig.3).
1998 Oct 23
5