TDA8732 Datasheet, PDF (5/14 Pages) NXP Semiconductors – NICAM-728 demodulator NIDEM

Philips Semiconductors
NICAM-728 demodulator (NIDEM)
Product specification
TDA8732
FUNCTIONAL DESCRIPTION
QPSK demodulator
The DQPSK signal input to the demodulator (QPSKIN) is
limited and fed into the costas loop demodulator. A
single-pin carrier oscillator (CAROSC), at twice the carrier
frequency, supplies a differential signal to the divider
circuitry, which drives the demodulators with both 0° and
90° phase shift. This produces cosine and sine signals
which are required for the carrier recovery. Cosine
(in-phase) and sine (in Quadrature) channel baseband
filters are then provided externally between pins CFO and
CFI, and SFO and SFI respectively. The two filtered
baseband signals are then processed to provide an error
signal, the magnitude and which of which bear a fixed
relationship to the phase error of the carrier, regardless of
which of the four rest-states the signal occupies. The
carrier recovery loop is closed with the aid of a single pin
loop filter connection at CARLPF, which filters the error
voltage signal to control the 728 kHz as shown in
application diagrams Fig.4 and 5.
Clock oscillator and timing generator
A voltage-controlled oscillator on-board the NIDEM
operates at 11.648 MHz and is divided down to produce a
728 kHz (bit-rate) clock output (CLK) which is phase
locked to the pulse stream and may be used as an
alternative clock input for NIDEM. A reference clock at
5.824 MHz is provided at pin C5M (TTL levels).
Differential decoder and parallel-to-serial converter
The recovered symbol-rate clocking-signal (364 kHz)
produced internally is passed to the demodulator where it
samples the sliced raised cosine pulse stream. The
recovered bit-rate clocking-signal is passed to the decoder
and is used to differentially decode the demodulated data
signal and reform it into a serial bit-stream.
Bit-rate clock recovery loop
The CFI and SFI channels are processed using edge
detectors and monostables, with externally derived time
constants (see Fig.3), to generate a signal with a coherent
component at the data bit symbol rate. This signal is
compared with the clock derived from CLKIN and used to
produce an error signal at the transconductance output
CLKLPF. This error signal is loop-filtered and used to
control the clock generator (at CLKOSC if the on-board
clock is used; see Fig.5).
April 1993
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