TDA8050 Datasheet, PDF (5/24 Pages) NXP Semiconductors – TDA8046H

Philips Semiconductors
QPSK transmitter
Product specification
TDA8050
FUNCTIONAL DESCRIPTION
The I and Q are balanced analog signals at a level of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator providing the modulated signal.
The modulated signal is then filtered by an IF filter. This
filtered signal together with a signal generated by a second
local oscillator is converted by a balanced mixer to
produce the QPSK signal.
The QPSK signal is amplified by a gain controlled amplifier
to a level suitable for transmission. The gain of the
controlled amplifier is bus controlled and this amplifier can
be disabled when not transmitting to provide signal
attenuation.
The amplified signal is applied to an on-chip amplifier
having two balanced outputs (open collector) linked to two
chip resistors (values 150 Ω), and 9 V. The balanced
outputs are designed to drive a 2 : 1 transformer
(Siemens V944) with a 75 Ω load giving an output level
of 55 dBmV. The output frequency range of the transmitter
is 5 to 40 MHz.
The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz) fixed by a Phase-Locked
Loop (PLL) implemented in the circuit.
The frequency of the second local oscillator operates in the
bandwidth 145 to 180 MHz and programmable due to a
PLL implemented in the circuit.
The VCO of both first and second local oscillators requires
an external LC tank circuit with two varicap diodes.
The data to the PLL is loaded in bursts framed by the
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns inactive (HIGH).
The last 14 bits are stored in the programming register.
No check is made on the number of clock pulses received
during the time programming is enabled. A wrong active
clock edge will be generated causing a shift of data
bits, if EN goes HIGH while CLK is still LOW. At power
up, EN should be HIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.
The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog Converter (DAC), the output amplifier
and the charge pump currents (Tables 1, 2 and 3).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V_CC
t_sc
V_max
V_o(tune)
V_o(buf)
P_tot
T_amb
T_stg
T_j(max)
PARAMETER
supply voltage
short-circuit time (every pin to V_CC or GND)
voltage on all pins except BUF_OUT, BUF_OUTC and TUNECONV
output tuning voltage
output buffer voltage on pins BUF_OUT and BUF_OUTC
maximum power dissipation
operating ambient temperature
storage temperature
junction temperature
MIN.
−0.3
−
−0.3
−0.3
−
−
0
−40
−
MAX.
+6.0
10
V_CC
+30
10
800
70
+150
150
UNIT
V
s
V
V
V
mW
°C
°C
°C
1999 Dec 14
5