PUSB2X4D_15 Datasheet, PDF (5/11 Pages) NXP Semiconductors – ESD protection for high-speed interfaces

NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
6
I_PP
(A)
4
aaa-009808
0
I_PP
(A)
-2
aaa-009809
2
-4
0
0
1
2
3
4
5
V_CL (V)
Fig 4.
IEC 61000-4-5; t_p = 8/20 s; positive pulse
Dynamic resistance with positive clamping;
typical values
15
I
(A)
12
aaa-009810
-6
-3
-2
-1
0
V_CL (V)
Fig 5.
IEC 61000-4-5; t_p = 8/20 s; negative pulse
Dynamic resistance with negative clamping,
typical values
0
I
(A)
-3
aaa-009811
9
-6
6
-9
3
-12
0
0
4
8
12
V_CL (V)
Fig 6.
t_p = 100 ns; Transmission Line Pulse (TLP)
Dynamic resistance with positive clamping,
typical values
-15
-8
-6
-4
-2
0
V_CL (V)
Fig 7.
t_p = 100 ns; Transmission Line Pulse (TLP)
Dynamic resistance with negative clamping;
typical values
The device uses an advanced clamping structure, which shows a negative dynamic
resistance. This snap-back behavior strongly reduces the clamping voltage to the system
behind the ESD protection during an ESD event. Do not connect unlimited DC current
sources to the data lines to avoid keeping the ESD protection device in snap-back state
after exceeding breakdown voltage (due to an ESD pulse for instance).
PUSB2X4D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 November 2013
© NXP B.V. 2013. All rights reserved.
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