PUCC3801 Datasheet, PDF (5/16 Pages) NXP Semiconductors – Current-mode PWM controller

Philips Semiconductors
PUCC3801
Current-mode PWM controller
With reference to Figure 4, assume that V_DD is rising slowly from zero to 12 V. The
Power Manager produces a Power-On Reset (POR) signal that is routed to every
flip-flop and counter in the device. This signal is made active as early as possible in
the power-up sequence to ensure that the internal logic is reset and the device
powers up in a known state.
The POR remains active until the bandgap reference voltage (V_bandgap) stabilizes and
the comparators in the power manager block have all settled into stable states. The
POR signal is then released and, once the supply voltage, V_DD reaches 10 V, the
controller section is enabled and the device starts to produce output pulses.
VDD
12.0
10.0
(V)
4.0
VDD
03af32
− 2.0
POR ^6.0
VREG ^5.0
VDD(comp)
(V) 2.0
− 1.0
3.0
2.5
Vbandgap
(V)
1.0
VDD(comp)
VREG
POR
Vbandgap
− 0.5
0
50
100
150
200
250
300
time
(µs)
Fig 4. Power-up sequence.
Over-voltage and under-voltage functions: Figure 5 shows the over-voltage trip
sequence.
1.2mA
IDD
70 µA
70 µA
1.2mA
VOUT
VDD
10 V
14 V
10 V
5V
regulated VDD = 12V
VREG ^{VREG = 3 V (off)}
VREG = 6 V (on)
3V
6V
03af33
Fig 5. Over-voltage and under-voltage functions.
A coarse internal supply V_REG is generated by the VREG section. In standby mode,
this supply drops to a low level, typically 3 V, and the current into the V_DD pin is limited
to a low value, less than 70 µA.
9397 750 08419
Product data
Rev. 01 — 10 September 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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