PHX1N40 Datasheet, PDF (5/7 Pages) NXP Semiconductors – PowerMOS transistor

Philips Semiconductors
PowerMOS transistor
Product specification
PHX1N40
Gate-Source voltage, VGS (Volts)
20
ID = 2.5 A
200 V
100 V
15
PHP2N40
VDD = 320 V
10
5
0
0
10
20
30
40
Gate charge, Qg (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
Switching times, td(on), tr, td(off), tf (ns)
1000
VDD = 200V
RD = 78 Ohms
Tj = 25 C
100
td(off)
tr
10 ^tf
td(on)
PHP2N40
1
0
20
40
60
80
100
Gate resistance, RG (Ohms)
Fig.14. Typical switching times.
t_d(on), t_r, t_d(off), t_f = f(R_G)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage.
V_(BR)DSS/V_{(BR)DSS 25 ˚C} = f(T_j)
10 ^{Source-drain diode current, IF(A)}
VGS = 0 V
8
150 C
6
PHP2N40
Tj = 25 C
4
2
0
0
0.5
1
1.5
Source-Drain voltage, VSDS (V)
Fig.16. Source-Drain diode characteristic.
I_F = f(V_SDS); parameter T_j
EAS, Normalised unclamped inductive energy (%)
120
110
100
90
80
70
60
50
40
30
20
10
0
20
40
60
80 100 120 140
Starting Tj ( C)
Fig.17. Normalised unclamped inductive energy.
E_AS% = f(T_j)
VGS
0
RGS
L
VDS
T.U.T.
+ ^VDD
-
-ID/100
R 01
shunt
Fig.18. Unclamped inductive test circuit.
E_AS = 0.5 ⋅ LI_D² ⋅ V_(BR)DSS/(V_(BR)DSS − V_DD)
June 1997
5
Rev 1.000